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| - 1 - k8a12(13)15et(b/z)c rev. 1.1, sep. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. 512mb c-die nor flash (32mb x16) synch burst, multi bank slc (1.7v ~ 1.95v) datasheet
- 2 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 revision history revision no. history draft date remark editor 1.0 - specification is fi nalized may. 03, 2010 final - 1.1 - added "clk "high" should be prohibited in asynchronous read mode start (from ce low)" in asynchronous read operation. sep. 06, 2010 final - - 3 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 512mb c-die nor flash 1 1.0 features................................................................................................................... .............................................. 4 2.0 general description ........................................................................................................ ................................. 4 3.0 pin description ............................................................................................................ ........................................ 4 4.0 ball fbga top view (ball down) ............................................................................................. ........................ 5 5.0 functional block diagram ................................................................................................... ........................... 6 6.0 ordering information ....................................................................................................... ............................... 7 7.0 product introduction....................................................................................................... ............................... 10 8.0 command definitions ........................................................................................................ ................................. 11 9.0 device operation ........................................................................................................... ..................................... 13 9.1 read mode .................................................................................................................. ............................................ 13 9.1.1.asynchronous read mode............ .............. .............. .............. .............. ........... ........... ......... ............................ 13 9.1.2.synchronous (burst) read mode ............. .............. .............. .............. .............. .............. ......... ......................... 13 9.2 programmable wait state .................................................................................................... ................................... 14 9.3 handshaking................................................................................................................ ............................................ 14 9.4 set burst mode configuration re gister ...................................................................................... ............................. 14 9.4.1.programmable wait stat e configuration.................................................................................... ...................... 14 9.4.2.burst read mode setting .................................................................................................. ............................... 15 9.4.3.rdy configuration ........................................................................................................ ................................... 15 9.5 output driver setting ...................................................................................................... ......................................... 16 9.6 autoselect mode............................................................................................................ .......................................... 16 9.7 standby mode ............................................................................................................... .......................................... 17 9.8 automatic sleep mode ....................................................................................................... ..................................... 17 9.9 output disable mode ........................................................................................................ ....................................... 17 9.10 block protection & unprotection ........................................................................................... ................................. 17 9.11 hardware reset........ .................................................................................................... ......................................... 17 9.12 software reset ............................................................................................................ .......................................... 17 9.13 program................................................................................................................... .............................................. 18 9.14 accelerated program..................................... .................................................................. ...................................... 18 9.15 write buffer programming .................................................................................................. ................................... 18 9.16 accelerated write buffer programming ................. ..................................................................... ........................... 19 9.17 chip erase ................................................................................................................ ............................................. 19 9.18 block erase ............................................................................................................... ............................................ 19 9.19 unlock bypass............................................................................................................. .......................................... 19 9.20 erase suspend / resume.................................................................................................... .................................. 20 9.21 program suspend / resume .................................................................................................. ............................... 20 9.22 read while write operation ................................................................................................ .................................. 20 9.23 otp block region .......................................................................................................... ....................................... 20 9.24 low vcc write inhibit ..................................................................................................... ...................................... 21 9.25 write pulse ?glitch? protection ........................................................................................... ................................... 21 9.26 logical inhibit........................................................................................................... .............................................. 21 10.0 flash memory status flags ................................................................................................. ........................ 22 11.0 deep power down ...... .............. .............. .............. .............. ........... ........... ............ ........... .................................. 25 12.0 common flash memory interface ............................................................................................. ................. 26 13.0 absolute maximum ratings ............................................................... ...................................................... 28 14.0 recommended operating condit ions (voltage reference to gnd) ...................................................... 28 15.0 dc characteristics ............................................................... ............................................................... ..... 29 16.0 capacitance (ta = 25 c, vcc = 1.8v, f = 1.0mhz) ............................................................... ....................... 31 17.0 ac test condition ............................................................... ............................................................... ........ 31 18.0 ac characteristics ........................................................................................................ .................................. 32 18.1 synchronous/burst read ............................................................... ............................................................... ...32 18.2 asynchronous read ............................................................... ............................................................... ..........35 18.3 erase/program operation ............................................................... ............................................................... ..39 18.4 erase/program performance ............................................................... ............................................................40 19.0 crossing of first word boundary in burst read mode ................................................................... 46 - 4 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 512m bit (32m x16) synch burst, multi bank slc nor flash memory 1.0 features ? single voltage, 1.7v to 1.95v for read and write operations ? organization - 33,554,432 x 16 bit (word mode only) ? read while program/erase operation ? multiple bank architecture - 16 banks (32mb partition) ? otp block : extra 512-word block ? read access time (@ cl=30pf) - asynchronous random access time : 100ns - synchronous random access time :95ns - burst access time : 11ns(66mhz) / 9ns(83mhz) / 7ns (108mhz) / 6ns (133mhz) ? page mode operation 16words page access allows fast asynchronous read page read access time : 18ns(66/83mhz) / 15ns(108/133mhz) ? burst length : - continuous linear burst - linear burst : 8-word & 16-word with wrap ? block architecture - uniform block part (k8a(10/11/12/13)15ezc) : five hundred twelve 64kword blocks - boot block part (k8a(10/11/12/13)15et(b)c) : four 16kword blocks and fi ve hundred eleven 64kwo rd blocks (bank 0 contains four 16 kword blocks and thir ty-one 64kword blocks, bank 1 ~ bank 15 contain four hundred eighty 64kword blocks) ? reduce program time using the vpp ? support 512-word buffer program ? power consumption (typical value, cl=30pf) - synchronous read current : 35ma - program/erase current : 25ma - read while program/erase current : 45ma - standby mode/auto sleep mode : 30ua ? block protection/unprotection - using the software command sequence - last two boot blocks are protected by wp =v il (boot block part : k8a(10/11/12/13)15et(b)c) - last one block (ba511) is protected by wp =v il (uniform block part : k8a(10/11/12/13)15ezc) - all blocks are protected by v pp =v il ? handshaking feature - provides host system with minimum latency by monitoring rdy ? erase suspend/resume ? program suspend/resume ? unlock bypass program/erase ? hardware reset (reset) ? deep power down mode ? data polling and toggle bits - provides a software method of detecting the status of program or erase completion ? endurance - 100k program/erase cycles minimum ? extended temperature : -25 c ~ 85 c ? support common flash memory interface ? output driver control by configuration register ? low vcc write inhibit ? package : tbd 2.0 general description the k8a(10/11/12/13)15e featuring single 1.8v power supply is a 512mbit muxed burst multi bank flash memory organized as 32mx16. the memory architecture of the device is designed to divide its memory arrays into 512blocks(uniform block part)/515blocks(boot block part) with indepen- dent hardware protection. this block arch itecture provides highly flexible erase and program capability. the k8a(10/11/12/13)15e nor flash con- sists of sixteen banks. this device is capable of reading data from one bank while programming or erasing in the other bank. regarding read access time, the k8a10/1215e provides an 11ns burst access time and an 95ns initial access time at 66mhz. at 83mhz, the k8a10/1215e provides an 9ns burst access time and an 95ns initial access time. at 108mhz, the k8a11/1315e provides an 7ns burst ac cess time and an 95ns initial access time. at 133mhz, the k8a11/1315e prov ides an 6ns burst access time and an 95ns initial access time. the device performs a program operation in units of 16 bits (word) and erases in units of a block. single or multiple blocks can be erased. the block erase operation is completed within typi- cally 0.6sec. the device requires 25ma as program/erase current in the extended temperature ranges. the k8a(10/11/12/13)15e nor flash memory is created by using sam- sung's advanced cmos process technology. 3.0 pin description pin name pin function a0 - a24 address inputs dq0 - dq15 data input/output ce chip enable oe output enable reset hardware reset pin v pp accelerates programming we write enable wp hardware write protection input clk clock rdy ready output avd address valid input dpd deep power down vcc power supply v ss ground - 5 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 4.0 ball fbga top view (ball down) tbd - 6 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 5.0 functional block diagram vcc vss ce oe we wp reset rdy interface & bank control x dec y dec latch & control latch & control dec x y dec erase control program control high voltage gen. bank 1 cell array bank 0 address bank 1 address bank 0 cell array avd x dec y dec latch & control bank 15 cell array block inform vpp bank 15 address clk i/o a0~a24 dq15 dq0~ dpd - 7 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 6.0 ordering information note : density : (1) 10 : 512mb for 66/83mhz with the sync mrs option (extended configuration register) (2) 11 : 512mb for 108/133mhz with the sync mrs option (extended configuration register) (3) 12 : 512mb for 66/83mhz with no option (4) 13 : 512mb for 108/133mhz with no option [table 1] product line-up [table 2] product classification [table 3] k8a(10/11/12/13)15e device bank divisions k8a(10/11/12/13)15e mode speed option 1c (66mhz) 1d (83mhz) 1e (108mhz) 1f (133mhz) v cc =1.7v -1.95v synchronous/ burst max. initial access time (t iaa, ns) 95 95 95 95 max. burst access time (t ba, ns) 11 9 7 6 asynchronous max. access time (t aa, ns) 100 100 100 100 max. ce access time (t ce, ns) 100 100 100 100 max. oe access time (t oe, ns) 15 15 15 15 speed/boot option top bottom uniform 512mb for 66/83mhz ( sync mrs option ) k8a1015etc k8a1015ebc k8a1015ezc 512mb for 108/133mhz ( sync mrs option ) k8a1115etc k8a1115ebc k8a1115ezc 512mb for 66/83mhz k8a1215etc k8a1215ebc K8A1215EZC 512mb for 108/133mhz k8a1315etc k8a1315ebc k8a1315ezc bank 0 ~ bank 15 type block sizes 512mbit (boot block part) four 16kword blocks and fi ve hundred eleven 64kword blocks 512mbit (uniform block part) five hundred twelve 64kword blocks k8 a 12 15 e t c - s e 1e samsung nor flash memory device type a : de-multiplexed burst density(*note) 10 : 512mbits for 66/83mhz (sync mrs) 11 : 512mbits for 108/133mhz (sync mrs) 12 : 512mbits for 66/83mhz (no option) 13 : 512mbits for 108/133mhz (no option) operating temperature range c : commercial temp. (0 c to 70 c) e : extended temp. (-25 c to 85 c) block architecture t : top boot block, b : bottom boot block z : uniform block version c : 4th generation access time 1e : refer to table 1 operating voltage range e : 1.7 v to 1.95v package f : fbga d : fbga(lead free) s : fbga(lead free, osp) organization 15 : x16 organization - 8 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 4] k8a(10/11/12/13)15ezc device bank divisions (uniform block) [table 5] k8a(10/11/12/13)15etc device bank divisions (top boot block) bank bank size quantity of blocks block size 0 32mb 32 64 kwords 1 32mb 32 64 kwords 2 32mb 32 64 kwords 3 32mb 32 64 kwords 4 32mb 32 64 kwords 5 32mb 32 64 kwords 6 32mb 32 64 kwords 7 32mb 32 64 kwords 8 32mb 32 64 kwords 9 32mb 32 64 kwords 10 32mb 32 64 kwords 11 32mb 32 64 kwords 12 32mb 32 64 kwords 13 32mb 32 64 kwords 14 32mb 32 64 kwords 15 32mb 32 64 kwords bank bank size quantity of blocks block size 0 32mb 4 16 kwords 31 64 kwords 1 32mb 32 64 kwords 2 32mb 32 64 kwords 3 32mb 32 64 kwords 4 32mb 32 64 kwords 5 32mb 32 64 kwords 6 32mb 32 64 kwords 7 32mb 32 64 kwords 8 32 64 kwords 32mb 9 32mb 32 64 kwords 10 32mb 32 64 kwords 11 32mb 32 64 kwords 12 32mb 32 64 kwords 13 32mb 32 64 kwords 14 32mb 32 64 kwords 15 32mb 32 64 kwords - 9 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 6] k8a(10/11/12/13)15ebc device bank divisions (bottom boot block) bank bank size quantity of blocks block size 15 32mb 32 64 kwords 14 32mb 32 64 kwords 13 32mb 32 64 kwords 12 32mb 32 64 kwords 11 32mb 32 64 kwords 10 32mb 32 64 kwords 9 32mb 32 64 kwords 8 32mb 32 64 kwords 7 32mb 32 64 kwords 32 64 kwords 632mb 5 32mb 32 64 kwords 4 32mb 32 64 kwords 3 32mb 32 64 kwords 2 32mb 32 64 kwords 1 32mb 32 64 kwords 032mb 31 64 kwords 4 16 kwords - 10 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 7.0 product introduction the k8a(10/11/12/13)15e is an 512mbit (536,870,912 bits) nor-type burst flash memory. the device features 1.8v single voltage p ower supply operat - ing within the range of 1.7v to 1.95v. the device is programm ed by using the channel hot electr on (che) injection mechanism whi ch is used to program eproms. the device is erased electrically by using fowler-nordheim tunneling mechanism . to provide highly flexible erase and pr ogram capability, the device adapts a block memory architecture th at divides its memory array into 512 bloc ks (64-kword x 512 blocks, uniform block p art) / 515 blocks (16- kword x 4 + 64-kword x 511, boot block part). programming is done in units of 16 bits (word). all bits of data in one or multip le blocks can be erased when the device executes the erase operati on. to prevent the device from accidental erasing or over-writing the programmed data , 512 / 515 memory blocks can be hardware protected. regarding read access time, at 66m hz, the k8a10/1215e provides a burst access of 11ns with in itial access times of 95ns at 30pf. at 83mhz, the k8a10/1215e provides a burst access of 9ns with initial access times of 95ns at 30pf. at 108mhz, th e k8a11/1315e pro - vides a burst access of 7ns with initial access times of 95ns at 30pf. at 133mhz, the k8a11/1315e provides a burst access of 6n s with initial access times of 95ns at 30pf. the command set of k8a(10/11/12/13)15e is compat ible with standard flas h devices. the device uses chip enable ( ce ), write enable ( we ), address valid( avd ) and output enable ( oe ) to control asynchronous read and write operati on. for burst operations, the device additionally requires ready (rdy) and clock (clk). devi ce operations are executed by selective command codes. the command codes to be combin ed with addresses and data are sequentially written to the command registers using microprocessor write ti ming. the command codes serve as inputs to an inter - nal state machine which controls the program/erase circuitry. register contents also internally latch addresses and data necess ary to execute the pro - gram and erase operations. the k8a(10/11/12/13)15e is implemented with internal program/erase routines to execute the program/e rase operations. the internal program/erase routines are invoked by program/eras e command sequences. the internal program routine automatically programs and verifies data at specified addresses. the internal erase routi ne automatically pre-programs the memory cell which is not progra mmed and then executes the erase operation. the k8a(10/11/12/13)15e has means to indicate the status of completion of program/erase operations. the st atus can be indicated via data polling of dq7, or the toggle bit (dq6). once the op erations have been completed, the device automatically resets itse lf to the read mode. the device requires only 35ma as burst and asynchronous mode read current and 25ma for buffer program/erase operations. [table 7] device bus operations note : l=vil (low), h=vih (high), x=don?t care. operation ce oe we a0-24 dq0-15 reset clk avd asynchronous read operation l l h add in i/o h l l write l h add in i/o h l x standby h x x x high-z h x x hardware reset xxx x high-z l x x load initial burst address l h h add in x h burst read operation l l h x burst d out hh terminate burst read cycle h x x x high-z h x x terminate burst read cycle via reset xxx x high-z l x x terminate current burst read cycle and start new burst read cycle l h h add in i/o h - 11 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 8.0 command definitions the k8a(10/11/12/13)15e operates by selecting and executing it s operational modes. each operational mode has its own command se t. in order to select a certain mode, a proper command with specific address and data s equences must be written into the command register. writing in correct information which include address and data or writing an improper command will reset the device to the read mode. the defined valid registe r command sequences are stated in table 8 . [table 8] command sequences command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle asynchronous read add 1 r a data rd reset 5),20) add 1 xxxh data f0h autoselect manufacturer id 6) add 4 555h 2aah (da)555h (da)x00h data aah 55h 90h ech autoselect device id 6) add 4 555h 2aah (da)555h (da)x01h data aah 55h 90h note6 autoselect block protection verify 7) add 4 555h 2aah (ba)555h (ba)x02h data aah 55h 90h 00h / 01h autoselect handshaking 6), 8) add 4 555h 2aah (da)555h (da)x03h d a t a a a h 5 5 h 9 0 h 0 h / 1 h program add 4 555h 2aah 555h pa data aah 55h a0h pd unlock bypass add 3 555h 2aah 555h data aah 55h 20h unlock bypass program 9) add 2 xxx pa data a0h pd unlock bypass block erase 9) add 2 xxx ba data 80h 30h unlock bypass chip erase 9) add 2 xxxh xxxh data 80h 10h unlock bypass reset add 2 xxxh xxxh data 90h 00h chip erase add 6 555h 2aah 555h 555h 2aah 555h data aah 55h 80h aah 55h 10h block erase add 6 555h 2aah 555h 555h 2aah ba data aah 55h 80h aah 55h 30h erase suspend 10) add 1 (da)xxxh data b0h erase resume 11) add 1 (da)xxxh data 30h program suspend 12) add 1 (da)xxxh data b0h program resume 11) add 1 (da)xxxh data 30h block protection/unprotection 13) add 3 xxx xxx abp data 60h 60h 60h cfi query 14) add 1 (da)x55h data 98h - 12 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 note : 1) ra : read address, pa : program address, rd : read data, pd : program data, ba : block address (a24 ~ a14), da : bank addres s (a24 ~ a21) abp : address of the block to be protected or unprotected, cr : configuration register setting wbl : write buffer location, wc : word count 2) the 4th cycle data of autoselect mode and rd are output data. the others are input data. 3) data bits dq15?dq8 are don?t care in command sequences, except for rd, pd and device id. 4) unless otherwise noted, address bits a24?a11 are don?t cares. 5) the reset command is required to return to read mode. if a bank entered the autoselect mo de during the erase suspend mode, writing the reset command returns that bank to the era se suspend mode. if a bank entered the autoselect mode during the program su spend mode, writing the reset command returns that bank to the p rogram suspend mode. if dq5 goes high during the program or erase operation, writ ing the reset command returns that bank to read mode or erase s uspend mode if that bank was in erase suspend mode. 6) the 3rd and 4th cycle bank address of autoselect mode must be same. device id data : "3013h" for top boot block device, "3014h" fo r bottom boot block device, "3015h" for uniform block device 7) normal block protection verify : 00h for an unprotected block and 01h for a protected block. otp block protect verify (with otp block address afte r entering otp block) : 00h for unlocked, and 01h for locked. 8) 0h for handshaking, 1h for non-handshaking 9) the unlock bypass command sequence is required prior to this command sequence. 10) the system may read and program in non-erasing blocks when in the erase suspend mode. the system may enter the autos elect mode when in the erase suspend mode. the erase suspend command is valid only duri ng a block erase operation, and requires the bank address. 11) the erase/program resume command is valid only during t he erase/program suspend mode, and requires the bank address. 12) this mode is used only to enable data read by suspending the program operation. 13) set abp(address of the block to be protected or unprotected) as either a6 = vih, a1 = vih and a0 = vil for unprotected or a 6 = vil, a1 = vih and a0 = vil for protected. 14) command is valid when the device is in read mode or autoselect mode. 15) for buffer program, firstly enter "write to buffer" command sequence and then enter block address and word count which is t he number of word data will be programmed. word count is smaller than the number of data wanted to program by one, example if 15 words are wanted to program then wc (word count) is 14. after entering command, enter pa/pd?s (program addresses/ program data). finally enter "progr am buffer to flash" command sequence, this starts a buffer program operation. this device supports 512-word buffer program. there is some caution points. - the number of pa/pd?s which are entered must be same to wc+1 - pa?s which are entered must be same a24~a9 address bi ts because buffer address is a24~a9 address and decided by pa ent ered firstly. - if pa which are entered isn?t same buffer address, then pa/pd which is entered may be ignored and this buffer programm ing operation is aborted. to return to normal operation, hardware reset or "write to buffer abort reset" command is issued. - overwrite for program buffer is also prohibited. 16) command sequence resets device for next command after aborted write-to-buffer operation . 17) see "set burst mode configuration register" for details. 18) on the third cycle, the data should be "c0h", address bits a10-a0 should be 101_0101_0101b, and address bits a21-a11 set th e code to be latched. 19) on the third cycle, the data should be "c5h", address bits a10-a0 should be 101_0101_0101b, and address bits a21-a11 set th e code to be latched. 20) after software reset and write to buffer abort reset command, min. 5us recovery time is needed for normal read mode. command definitions cycle 1st cycle 2nd cycle 3rd cycle 4th cycle 5th cycle 6th cycle write to buffer 15) add 3 555h 2aah ba ba pa wbl data aah 55h 25h wc pd pd program buffer to flash 15) add 1 ba data 29h write to buffer abort reset 16),20) add 3 555h 2aah xxx data aah 55h f0h set burst mode configuration register 17),18) add 3 555h 2aah note 18 data aah 55h c0h set extended configuration register 17),19) add 3 555h 2aah note 19 data aah 55h c5h enter otp block region add 3 555h 2aah xxx data aah 55h 70h exit otp block region add 4 555h 2aah 555h xxx data aah 55h 75h 00h - 13 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.0 device operation the device has inputs/outputs that accept both address and data information. to write a command or command sequence (which incl udes programming data to the device and erasing blocks of memory), the system mu st drive clk, we and ce to vil and oe to vih when writing comman ds or data. the device provides the unlock bypass mode to save its program ti me for program operation. unlike the standard program command sequ ence which is com - prised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. one block, multipl e blocks, or the entire device can be erased. table 17 indicates the address space that each block occupies. the dev ice?s address space is divided into sixteen banks. a ?bank address? is the address bits required to uniquely select a bank. simi larly, a ?block address? is the address bits required to u niquely select a block. icc2 in the dc characteristics table represents the ac tive current specification for the write mode. the ac characteristics section con tains timing specification tables and timing diagrams for write operations. 9.1 read mode the device automatically enters to asynchronous read mode after device power-up. for synchronous read, the device needs to be s et mode register prior to read operation. after completing an internal program/erase r outine, each bank is ready to read array data. the reset command is required to return a bank to the read(or erase-suspend-read)mode if dq5 goes high during an active program/erase operation, or if the bank is in the autoselect mode. (1) k8a1015et(b)(z)c : 66/83mhz with the sync mrs option (extended configuration register) (2) k8a1115et(b)(z)c : 108/133mhz with the sync mrs option (extended configuration register) the synchronous(burst) mode will automatically star t on the rising edge of the clk input while avd is held low after extended mode register setting to a13=0, a12=1. if several clks exist in avd low, the last rising edge is valid clk. (3) k8a1215et(b)(z)c : 66/83mhz with no option (4) k8a1315et(b)(z)c : 108/133mhz with no option the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low. if several clks exist in avd low, the last rising edge is valid clk. 9.1.1. asynchronous read mode for the asynchronous read mode a valid address should be asserted on a0-a24, while driving avd and ce to vil. we should remain at vih. the data will appear on dq0-dq15. since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. address access time (taa) is equal to the delay from valid addresses to valid output data. the chip enable access time(tce) is the delay from the falling edge of ce to valid data at the outputs. the output enable access ti me(toe) is the delay from the falling edge of oe to valid d ata at the output. to prevent the memory content from spurious alteri ng during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. 9.1.1.1 . asynchronous page read mode 16-words page mode is supported for fast asynchronous read. af ter address access time(taa), sixteen data words are loaded into an internal page buf - fer. a0~a3 bits determine which page word is output during a read operation. a4~a24 and avd must be stable throughout the page read access. figure 11 shows the asynchronous page read mode timing. 9.1.2. synchronous (burst) read mode the device is capable of continuous linear burst operation and linear burst operation of a preset length. for the burst mode, t he system should determine how many clock cycles ar e desired for the initial word(tiaa) of each burst access and what mode of burst operation is desired u sing "burst mode config - uration register" command sequences. see "set burst mode configur ation" for further details. the status data also can be read d uring burst read mode by using avd signal with a bank address which is programming or erasing. to initiate the synchronous read again, a new address and avd pulse is needed after the host has completed status reads or the device has completed the program or erase operation. 9.1.2.1 . continuous linear burst read (1) k8a1015et(b)(z)c : 66/83mhz with the sync mrs option (extended configuration register) (2) k8a1115et(b)(z)c : 108/133mhz with the sync mrs option (extended configuration register) the synchronous(burst) mode will automatically star t on the rising edge of the clk input while avd is held low after extended mode register setting to a13=0, a12=1. if several clks exist in avd low, the last rising edge is valid clk. (3) k8a1215et(b)(z)c : 66/83mhz with no option (4) k8a1315et(b)(z)c : 108/133mhz with no option the synchronous(burst) mode will automatically start on the rising edge of the clk input while avd is held low. if several clks exist in avd low, the last rising edge is valid clk. the initial word is output tiaa after the rising edge of the last clk cycle. subsequent words are output tba after the rising e dge of each successive clock cycle, which automaticall y increase the internal address counter. note that the device has internal address boundary that occur s every 16 words. when the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. th e number of additional clock cycle can vary from zero to thir teen cycles, and the exact number of additi onal clock cycle depends on the starting addre ss of burst read. the rdy output indicates this condition to the syst em by pulsing low. the device will cont inue to output sequential burst data, wrappin g around to address 0000000h after it reaches the highest addressable memory lo cation until the system asserts ce high, reset low or avd low in conjunction with a new address.(refer to table 7 .) the reset command does not terminate the burst read operation. when it accesses the bank is programming or erasing, con - tinuous burst read mode will output status data. and status data will be sustained until the system asserts ce high or reset lo w or avd low in conjuction with a new address. note that at least 10ns is needed to start ne xt burst read operation from terminating previous burst read o peration in the case of asserting ce high. - 14 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 8-, 16-word linear burst read as well as the continuous linear burst mode, there are two(8 & 16 word) linear wrap, in which a fixed number of words are read from consecutive addresses. in these modes, the addresses for burst read are det ermined by the group within which the starting address falls. th e groups are sized according to the number of words read in a sing le burst sequence for a given mode. (refer to ta b l e 9 ) [table 9] burst address groups (wrap mode) as an example: in wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be 2-3-4-5-6-7-0-1h. the burst sequence begins with the starting address written to the device, but wraps back t o the first address in the selected group. in a similar manner, 16-word wrap mode begins it s burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. 9.2 programmable wait state the programmable wait state feature indicates to the device th e number of additional clock cycles that must elapse after avd is driven from low to high for burst read mode. upon power up, the number of total initial access cycles defaults to fourteen. 9.3 handshaking the handshaking feature allows the host syst em to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initial cycle for optimal bur st mode, the host should use the programmable wait state configur ation.(see "set burst mode configuration register" for details.) the rising edge of rdy after oe goes low indicates the initial word of valid burst data.( rdy can be low active by extended configuration register a11 setting : rdy low indicates data valid) using t he autoselect command sequence, the handshak ing feature will be ver - ified in the device. 9.4 set burst mode configuration register the device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. the burst mode configuration register must be set before the device enters burst mode. the burst m ode configuration register is loaded with a three-cycle command sequences. on the third cycle, the data should be c0h, addre ss bits a10-a0 should be 101_0101_0101b, and address bits a21-a11 s et the code to be latched. the device returns to default setting after power up or hardware reset. 9.4.1. programmable wait state configuration this feature informs the device the number of clock cycles that must elapse after avd is driven from low to high before data will be available. this value is determined by the input frequency of t he device. address bits a14-a11 determine the setting. (see configuration register table 10 .) the programma - ble wait state setting instructs the device to set a particular num ber of clock cycles for the initial access in burst mode. no te that hardware reset will revert the wait state to the default setting, that is 14 initial cycles. burst mode group size group address ranges 8 word 8 words 0-7h, 8-fh, 10-17h, .... 16 word 16 words 0-fh, 10-1fh, 20-2fh, .... - 15 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.4.2. burst read mode setting the device supports three different burst read modes : conti nuous linear mode, 8 and 16 word linear burst modes with wrap. 9.4.3. rdy configuration by default, the rdy pin will be high whenever there is valid dat a on the output. (rdy can be low active by configuration regist er a11 setting : rdy low indicates data valid) the device can be set so that rdy goes acti ve one data cycle before active data. address bit a18 determin es this setting. the rdy pin behaves same way in wo rd boundary crossing case. [table 10] burst mode configuration register table note : initial wait state should be set according to it?s clock frequency. table 10 recommend the program wait state for each clock fr equencies. not 100% tested [table 11] extended configuration register table note : default mode is asynchronous read mode. (a13=0, a12=0) in this mode device is still in asynchronous read even if it is in clk r ising while avd low condition. to use synchronous read mode, user should set extended configuration register (a13=0, a12=1). in this mode both of asynchronous and synchronous read mode is available. the synchronous (burst) mode should be started on the last rising edge of the clk input while avd is held low after extended mode register setting to a13=0, a12=1. address bit function settings (binary) a21 output driver control 000 = setting 0 001 = setting 1 010 = setting 2 (reserve) 011 = setting 3 (reserve) 100 = setting 4 (default) 101 = setting 5 (reserve) 110 = setting 6 (reserve) 111 = setting 7 a20 a19 a18 rdy active 0 = rdy active with data (default) 1 = rdy active one clock cycle before data a17 burst read mode 000 = continuous (default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 ~ 111 = reserve a16 a15 a14 programmable wait state 0000 = data is valid on the 4th active clk edge after avd transition to vih 0001 = data is valid on the 5th active clk edge after avd transition to vih (40mhz*) 0010 = data is valid on the 6th active clk edge after avd transition to vih (50/54mhz*) 0011 = data is valid on the 7th active clk edge after avd transition to vih (60/66mhz*) 0100 = data is valid on the 8th active clk edge after avd transition to vih (70mhz*) 0101 = data is valid on the 9th active clk edge after avd transition to vih (80/83mhz*) 0110 = data is valid on the 10th active clk edge after avd transition to vih (90/100mhz*) 0111 = data is valid on the 11th active clk edge after avd transition to vih (108/110mhz*) 1000 = data is valid on the 12th active clk edge after avd transition to vih (120mhz*) 1001 = data is valid on the 13th active clk edge after avd transition to vih (133mhz*,default) 1010 = data is valid on the 14th active clk edge after avd transition to vih 1011 = data is valid on the 15th active clk edge after avd transition to vih 1100 ~1111 = reserve a13 a12 a11 address bit function settings (binary) a13 read mode 00 = asynchronous read mode(default) 01 = synchronous burst read mode 10 ~ 11 = reserve a12 a11 rdy polarity 0 = rdy signal is active high (default) 1 = rdy signal is active low - 16 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 12] burst address sequences 9.5 output driver setting the device supports four kinds of output dr iver setting for matching the system charac teristics. the users can tune the output driver impedance of the data and rdy outputs by address bits a21-a19. (see configuration register table) table 13 shows which output driver would be tuned and the strength according to a21-a19. upon power-up or reset, t he register will revert to the default setting. [table 13] output driver setting table 9.6 autoselect mode by writing the autoselect command sequences to the system, the dev ice enters the autoselect mode. this mode can be read only by asynchronous read mode. the system can then read autoselect codes from the internal register (which is separate from the memory array). standard asynchronous read cycle timings apply in this mode. the device offers the autosele ct mode to identify manufacturer and device type by reading a b inary code. in addition, this mode allows the host system to ve rify the block protection or unprotection. table 14 shows the address and data requirements. the autoselect com - mand sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-r ead mode. the autoselect command may not be written while t he device is actively programming or eras ing in the device. the autoselect command sequence is initiated by first writing two unlock cycl es. this is followed by a thir d write cycle that contains th e address and the autoselect comman d. note that the block address is needed for the verification of bloc k protection. the system may read at any address within the same bank any number of times without initiat - ing another autoselect command sequence. and the burst read should be prohibited during autoselect mode. to terminate the autos elect operation, write reset command(f0h) into the command register. [table 14] autoselect mode description start addr. burst address sequence continuous burst 8-word burst 16-word burst wrap 0 0-1-2-3-4-5-6... 0-1-2-3-4-5-6-7 0-1-2-3 ... -d-e-f 1 1-2-3-4-5-6-7... 1-2-3-4-5-6-7-0 1-2-3-4 ... -e-f-0 2 2-3-4-5-6-7-8... 2-3-4-5-6-7-0-1 2-3-4-5 ... -f-0-1 . . . . . . . . address bits value function a21-a19 000 driver multiplier : 1/3 001 driver multiplier : 1/2 010 reserve 011 reserve 100 driver multiplier : 1 (default) 101 reserve 110 reserve 111 driver multiplier : 1.5 description address read data manufacturer id (da) + 00h ech device id (da) + 01h 3013h (top boot block), 3014h (bottom boot block), 3015h (uniform block) block protection/unprotection (ba) + 02h 01h (protected), 00h (unprotected) handshaking (da) + 03h 0h : handshaking, 1h : non-handshaking - 17 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.7 standby mode when the ce inputs is held at vcc 0.2v, and the system is not reading or writing, the device enters stand-by mode to minimize the power consumption. in this mode, the device outputs are placed in the high impedenc e state, independent of the oe input. when the device is in eit her of these standby modes, the device requires standard access ti me (tce) for read access before it is r eady to read data. if the device is deselec ted during erasure or pro - gramming, the device draws active current until the operation is co mpleted. icc5 in the dc characteristics table represents the standby current specifica - tion. 9.8 automatic sleep mode the device features automatic sleep mode to minimize the device power consumption during both asynchronous and burst mode. when addresses remain stable for taa+60ns, the device automatically enables th is mode. the automatic sleep mode is depends on the ce, we and o e signal, so ce, we and oe signals are held at any state. in a sleep mode, output data is latched and always avail able to the system. when oe is active, the device pro - vides new data without wait time. automatic sl eep mode current is equal to standby mode current. 9.9 output disable mode when the oe input is at vih, output from the device is disabled. the outputs are placed in the high impedance state. 9.10 block protection & unprotection to protect the block from accidental writ es, the block protection/unprotection command sequence is used. on power up, all block s in the device are pro - tected. to unprotect a block, the system must write the bloc k protection/unprotection command s equence. the first two cycles ar e written: addresses are don?t care and data is 60h. using the third cycle, the block addr ess (abp) and command (60h) is written, while specifying with addresses a6, a1 and a0 whether that block should be protected (a6 = vil, a1 = vih, a0 = vil) or unprotected (a6 = vih, a1 = vih, a0 = vil). after the third cycle, the system can continue to protect or unprotect additi onal cycles, or exit the sequence by writing f0h (reset command). the device offers three types of data protection at the block level: ? the block protection/unprotection command sequence disables or re-enables both program and erase operations in any block. ? when wp is at v il , the two outermost blocks are protected.(boot block part : k8a(10/11/12/13)15et(b)c) ? when wp is at v il , the last one block (ba511) is protected.(u niform block part :k8a(10/11/12/13)15ezc) ? when v pp is at v il , all blocks are protected. note that user never float the vpp and wp, that is, vpp is always connected with vih, vil or vid and wp is vih or vil. 9.11 hardware reset the device features a hardware method of resetting the device by the reset input. when the reset pin is held low(vil) for at le ast a period of trp, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the dur ation of the reset pulse. the device also resets the internal state machine to asynch ronous read mode. to ensure data integrity, the interrupted operatio n should be reinitiated once the device is ready to acce pt another command sequence. the reset pin may be tied to the system reset pin. if a system res et occurs during the internal program or erase routine, the device will be automatic ally reset to the asynchronous read mode; this will enable the s ystems microprocessor to read the boot-up firmware from the flash memory. if reset is as serted during a program or erase operation, the device requires a time of tready (dur - ing internal routines) before the device is ready to read data again. if reset is as serted when a program or erase operation is not executing, the reset operation is completed within a time of tready (not during inte rnal routines). trh is needed to read data after reset returns t o vih. refer to the ac characteristics tables for reset parameters and to figure 12 for the timing diagram. when reset is at logic high, the device is in standard operation. when reset transitions from logi c-low to logic-high, the device resets all bloc ks to locked and defaults to the read array mode . 9.12 software reset the reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. the add resses are in don?t care state. the reset command may be written between the sequence cycles in an erase co mmand sequence before erasing begi ns, or in an pro - gram command sequence before programming begins . if the device begins erasure or progra mming, the reset command is ignored unti l the operation is completed. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command re turns that bank to the erase-suspend-read mode. the reset command valid between the s equence cycles in an autoselect command sequence. in an autoselec t mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase suspend mode , writing the reset command returns that bank to the erase-suspend-read mode. also, if a bank entered the autoselect mode while in the program susp end mode, writing the reset command returns that bank to the program-suspend-read m ode. if dq5 goes high during a program or erase operation, wri ting the reset com - mand returns the banks to the read mode. (or erase-suspend-read mode if the bank was in erase suspend) - 18 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.13 program the k8a(10/11/12/13)15e can be programmed in units of a word. pr ogramming is writing 0's into the memory array by executing the internal program routine. in order to perform the internal program routine, a four-cycle command sequence is necessary. the first two cycles are unlock cycles. the third cycle is assigned for the program setup comm and. in the last cycle, the address of the memory location and the data to be progr ammed at that location are written. the device automatically generates adequate program pu lses and verifies the programmed cell margin by the internal program routine. dur - ing the execution of the routine, the system is not required to provide further controls or timings. during the internal progra m routine, commands written to the device will be ignored. note that a hardware reset during a program operation wi ll cause data corruption at the corresponding location. 9.14 accelerated program the device provides accelerated program operations through the vpp input. using this mode, faster manufacturing throughput at t he factory is possible. when vid is asserted on the vpp input, the dev ice automatically enters the unlock bypass mode, temporarily unprotects any prote cted blocks, and uses the higher voltage on the input to reduce the time required for pr ogram operations. in accelerated program mode, the system wou ld use a two-cycle pro - gram command sequence for only a word program. by remo ving vid returns the device to normal operation mode. note that read while accelerated program (erase) and program suspend (erase suspend) mode are not guaranteed. ? program/erase cycling must be limited below 100cycles for optimum performance. ? ambient temperature requirements : ta = 30 c10 c 9.15 write buffer programming write buffer programming allows the system write to a maximum of 512-word in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is in iti-ated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer l oad command written at the block address in which programming will occur. the fourth cycle writes the block address and the number of word locations, minus one, to be programmed. for example, if the system will program 19 unique address locations, then 12h should be written to the device. this tell s the device how many write buffer addresses will be loaded with data. the number of loca - tions to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first addre ss location and data to be pro - grammed. the write-buffer-page is selected by address bits a24(max.) ~ a9 entered at fifth cycle. all subsequent address/ data pairs must fall within the selected write-buffer-page, so that all subsequent addresses must have the same address bit a24(max.) ~ a9 as those entered at fifth cycle. write buffer locations may be loaded in any order. once the specified number of write buffer locations have been loaded, the system must then write the "program buffer to flash" command at the block address. any other command address/data combination aborts the wr ite buffer programming operation. the device then begins progr amming. data poll - ing should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be mo nitored to determine the device status during write buffer programming. the writ e-buffer programming operation can be suspended using the standard p rogram suspend/ resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. note also that an address location cannot be loaded more than once into the write-buffer-page. the write buffer programming sequence can be aborted in the following ways: ? loading a value that is greater than the buffer size(512-word ) during then number of word locations to program step. (in case, wc > 1ffh @ table 8 ) ? the number of program address/data pairs entered is different to the number of word locations initially defined with wc (@ table 8 ) ? writing a program address to have a different write-buffer-page with selected write-buffer-page ( address bits a24(max) ~ a9 are different) ? writing non-exact "program buffer to flash" command the abort condition is indicated by dq1 = 1, dq7 = data (for the last address location loaded), dq6 = toggle, and dq5=0. a "wri te-to-buffer-abort reset" command sequence must be written to reset the device for t he next operation. note that the third cycle of write-to-buffe r-abort reset command sequence is required when using write-buffer-pr ogramming features in unlock bypass mode. and from the third cycle to the last cycle of write to buff er command is also required when using write-buffer-programming fea tures in unlock bypass mode. a bit cannot be programmed from ?0? back to a ?1.? attempti ng to do so may cause the dq7 and dq6 status bits to indicate the operation was suc - cessful. however, a succeeding read will s how that the data is still ?0.? only erase operations can convert a ?0? to a ?1." - 19 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.16 accelerated write buffer programming the device provides accelerated write buffer program operations through the vpp input. using this mode, faster manufacturing th roughput at the factory is possible. when vid is asserted on the vpp input, the device temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. in accelerated writ e buffer program mode, the system must enter "write to buf fer" and "program buffer to flash" command sequence to be same as them of normal write buff er programming. note that the third cycle of "write to buffer abort reset" com - mand sequence is required in an accelerated mode. note that read while accelerated write buffer program and program suspend mode are not guaranteed. ? program/erase cycling must be limited below 100cycles for optimum performance. ? ambient temperature requirements : ta = 30 c10 c 9.17 chip erase to erase a chip is to write 1 s into the entire memory array by executing the internal erase routine. the chip erase requires six bus cycles to write the command sequence. the erase set-up command is wr itten after first two "unlock" cycles. t hen, there are two more write cycles pr ior to writing the chip erase command. the internal erase routine automatically pre-progr ams and verifies the entire memory for an all zero data patter n prior to erasing. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminat es when dq7 is "1". after th at the device returns to the read mode. 9.18 block erase to erase a block is to write 1 s into the desired memory block by executing the internal eras e routine. the block erase requi res six bus cycles to write the command sequence shown in table 8 . after the first two "unlock" cycles, the erase setup command (80h) is wri tten at the third cycle. then there are two more "unlock" cycles followed by the bl ock erase command. the internal erase routi ne automatically pre-programs and verifies th e entire memory prior to erasing it. multiple blocks can be eras ed sequentially by writing the sixth bus-cycle . upon completion of the last cycle for the block erase, additional block address and the block erase command (30h ) can be written to perform the multi-block erase. for the multi-block erase, onl y sixth cycle(block address and 30h) is needed.(similarly, only sec ond cycle is needed in unlock by pass block erase.) an 50us (typical) "time windo w" is required between the block erase command writes. the block er ase command must be written within the 50us "time window", otherwise the block eras e command will be ignored. the 50us "time window" is reset when the falling edge of t he we occurs within the 50us of "time window" to latch the b lock erase command. during the 50us of "time window", any command other than the block erase or the erase suspend co mmand written to the device wil l reset the device to read mode. after the 50 us of "time window", the block erase comm and will initiate the internal erase routine to erase the sele cted blocks. any block erase address and command following the exceeded "time window" may or may not be accepted. no other commands will be recognized except the erase suspend command during block erase operation. 9.19 unlock bypass the k8a(10/11/12/13)15e provides the unlock bypass mode to save its operation time. this mode is possible for program, block er ase, chip erase, write to buffer and write to buffer abort reset operation. there are two methods to enter the unlock bypa ss mode. the mode is invoked by the unlock bypass command sequence or the assertion of vid on vpp pin. unlike the st andard program/erase command sequ ence that contains four bus cycles, the unlock bypass program/erase command sequence comprises only two bus cy cles. the unlock bypass mode is engaged by issuing the unlock by pass command sequence which is comprised of three bus c ycles. writing first two unlock cycles is fo llowed by a third cycl e containing the un lock bypass command (20h). once the device is in the unlock bypass mode, the unlock bypa ss program/erase command sequence is necessary. the unlock bypass program com - mand sequence is comprised of only two bus cycles; writing the unlock bypass program command (a0h) is followed by the program a ddress and data. this command sequence is the only valid one for programming the dev ice in the unlock bypass mode. also, the unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80h-30h) or writing the unlock bypass ch ip erase com - mand(80h-10h). this command sequences are t he only valid ones for erasing the device in the unlock bypass mode. the unlock bypa ss reset command sequence is the only valid co mmand sequence to exit the unlock bypass mode. th e unlock bypass reset command sequence consists o f two bus cycles. the first cycle must contain the data (90h). the second cycle co ntains only the data (00h). then, the device returns to the rea d mode. to enter the unlock bypass mode in hardware level, the vid also can be used. by assertion vid on the vpp pin, the device enters the unlock bypass mode. also, the all blocks are temporarily unprotected when the device using the vi d for unlock bypass mode. to exit the unlock bypass mode, just remove the asserted vid from the vpp pin.(note that user never float the vpp, that is, vpp is always connected with vih, vil or vid.). - 20 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.20 erase suspend / resume the erase suspend command interrupts the block erase to read or pr ogram data in a block that is not being erased. also, it is p ossible to protect or unprotect of the block that is not being erased in erase suspend mode. the erase su spend command is only valid during the block erase operation including the time window of 50us. the erase suspend command is not valid while the chip erase or the internal program routine sequence is running. when the erase suspend command is written during a block erase oper ation, the device requires a maximum of 30us(recovery time) to suspend the erase operation. therefore system must wait for 30us(recovery ti me) to read the data from the bank which include the block bein g erased. otherwise, system can read the data immediately from a bank which don?t include the block being erased without recovery time(max. 30us) af ter erase suspend command. and, after the maximum 30us recovery time, the device is availble for programming data in a block that is not being er ased. but, when the erase suspend command is written during the block erase time window (50us), the device terminates the block erase time window a nd suspends the erase operation in about 2us. the system may also write the aut oselect command sequence when the device is in the erase suspend mode. when the erase resume command is executed, the bloc k erase operation will resume. when the eras e suspend or erase resume command is exec uted, the addresses are in the bank address which is operating in erase suspend or erase resume. while erase can be suspended and resumed multiple times, a minimum 30us is required from resume to the next suspend. 9.21 program suspend / resume the device provides the program suspend/resu me mode. this mode is used to enable data read by suspending the program operation. the device accepts a program suspend command in program mode (including pr ogram operations performed during erase suspend) but other comma nds are ignored. after input of the program suspend command, 5us is needed to enter the program suspend read mode. therefore system mus t wait for 5us(recovery time) to read the data from t he bank which include the block being programm ed. otherwise, system can read the data immediately from a bank which don't include block being programm ed without recovery time (max. 5us) afte r program suspend command. like an erase s uspend mode, the device can be returned to program m ode by using a program resume command. in the program suspend mode, protect/unprotect command is prohibited. while program can be suspended and resumed multiple times, a mi nimum 30us is required from resume to the next suspend. 9.22 read while write operation the device is capable of reading data from one bank while writi ng in the other banks. this is so called the read while write op eration. an erase operation may also be suspended to read from or program to another location within the same bank (except the block being erased). the rea d while write opera - tion is prohibited during the chip erase operation. figure 19 s hows how read and write cycles may be initiated for simultaneous operation with zero latency. refer to the dc characteristics tabl e for read-while-write current specifications. 9.23 otp block region the otp block feature provides a 512-word flash memory region that enables permanent part identification through an electronic serial number (esn). the otp block is customer lockable and shi pped with itself unlocked, allowing customer s to untilize the that block in any manne r they choose. the cus - tomer-lockable otp block has the protection verify bit (dq0) set to a "0" for unlocked state or a "1" for locked state. the system accesses the otp block through a command sequence (see "enter otp block / exit ot p block command sequence" at table 8 ). after the system has written the "enter otp block" command sequence, it may read the ot p block by using the addresses (1fffe00h~1ffffffh : top boot block device/uniform block device, 0000000h-00001ffh : bottom boot block device) normally and may c heck the protection verify b it (dq0) by using the "autoselect block protection ve rify" command sequence with otp block address. this mode of operation continues until the system issues the "exit otp block" command suquence, a hardware reset or until power is re moved from the device. on power-up, or following a hardware r eset, the device reverts to sending commands to main blocks. note that the acce lerated function and unlock bypass modes are not available when t he otp block is enabled. customer lockable in a customer lockable device, the otp block is one-time progr ammable and can be locked only once. note that the accelerated pr ogramming and unlock bypass functions are not availabl e when programming the otp block. locking operat ion to the otp block is started by writ ing the "enter otp block" command sequence, and then the "block protection" command seqeunce ( table 8 ) with an otp block address. t he locking operation has to be above 100us. "exit otp block" command sequence and hardware reset ma kes locking operation finished and then exiting from otp bl ock after 30us. the otp block lock operation must be used wi th caution since, once locked, there is no procedure available for unlocking and no ne of the bits in the otp block space can be modified in any way. suspend and resume operation are not supported during otp protec t, nor is otp protect supported during any suspend operations. after entering otp block, program/erase operation on main blocks is prohibited. enter otp block command is not allowed while ot her operation is excut - ing. - 21 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 9.24 low v cc write inhibit to avoid initiation of a write cycle during vcc power-up and powe r-down, a write cycle is locked out for vcc less than vlko. if the vcc < vlko (lock-out voltage), the command register and all internal program/erase circ uits are disabled. under this condition the device will reset itself to the read mode.sub - sequent writes will be ignored until the vcc level is greater than vlko. it is the user?s responsibility to ensure that the con trol pins are logically correct to prevent unintentional writes when vcc is above vlko. 9.25 write pulse glitch protection noise pulses of less than 5ns (typical) on oe, ce, avd or we do not initiate a write cycle. 9.26 logical inhibit write cycles are inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle, ce and we must be a logical zero while oe is a logical one - 22 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 10.0 flash memory status flags the k8a(10/11/12/13)15e has means to indicate its status of ope ration in the bank where a program or erase operation is in proc esses. address must include bank address being executed internal routine operation. the status is indicated by raisi ng the device status flag via c orresponding dq pins. the status data can be read during burst read mode by using avd signal with a bank address. that means status read is supported in synchronous mode. if status read is performed, the data provided in the burst read is identical to the data in the initial access. to initiate the s ynchronous read again, a new address and avd pulse is needed after the host has completed status reads or t he device has completed the program or erase operation. the corr e - sponding dq pins are dq7, dq 6, dq5, dq3, dq2 and dq1. [table 15] hardware sequence flags note : 1) dq2 will toggle when the device performs successive read operations from the erase/program suspended block. 2) if dq5 is high (exceeded timing limits), successive reads from a problem block will cause dq2 to toggle. 3) note that dq7 during write-to-buffer-programming indicates the data-bar for dq7 data for the last loaded write-buffer addres s location. status dq7 dq6 dq5 dq3 dq2 dq1 in progress programming dq7 toggle 0 0 1 0 block erase or chip erase 0 toggle 0 1 toggle 0 erase suspend read erase suspended block 1 1 0 0 toggle 1) 0 erase suspend read non-erase suspended block data data data data data data erase suspend program non-erase suspended block dq7 toggle 0 0 1 0 program suspend read program suspended block dq7 1 0 0 toggle 1) 0 program suspend read non- program suspended block data data data data data data exceeded time limits programming dq7 toggle 1 0 no toggle 0 block erase or chip erase 0 toggle 1 1 note2 0 erase suspend program dq7 toggle 1 0 no toggle 0 write-to- buffer 3) busy state dq7 toggle 0 0 no toggle 0 exceeded timing limits dq7 toggle 1 0 no toggle 0 abort state dq7 toggle 0 0 no toggle 1 - 23 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 dq7 : data polling when an attempt to read the device is made while executing the inte rnal program, the complement of the data is written to dq7 a s an indication of the routine in progress. when the routine is completed an attempt to access to the device will produce the true data written to dq7 . when a user attempts to read the block being erased or bank contains the block, dq7 wi ll be low. if the device is placed in the erase/program suspen d mode, the status can be detected via the dq7 pin. if the system tries to read an addres s which belongs to a block that is being erase suspended, dq7 wi ll be high. and, if the sys - tem tries to read an address which belongs to a block that is being program suspended, the output will be the true data of dq7 itself. if a non-erase-sus - pended or non-program-suspended block address is read, the device wi ll produce the true data to dq7. if an attempt is made to p rogram a protected block, dq7 outputs complements the data for approximately 2us and the device then returns to the read mode without changing dat a in the block. if an attempt is made to erase a protected block, dq7 outputs comple ment data in approximately 100us and the device then returns to t he read mode without erasing the data in the block. dq6 : toggle bit toggle bit is another option to detect whether an internal routine is in progress or co mpleted. once the device is at a busy st ate, dq6 will toggle. toggling dq6 will stop after the device completes it s internal routine. if the device is in the erase/program suspend mode, an attempt t o read an address that belongs to a block that is being erased or programmed will produce a high output of dq6. if an address belongs to a block that is not being erased or pro - grammed, toggling is halted and valid data is produced at dq6. if an attempt is made to program a protected block, dq6 toggles for approximately 2us and the device then returns to the read mode without changing the data in the block. if an attempt is made to erase a protected block, dq6 toggles for approximately 100 s and the device then returns to the read mode without erasing th e data in the block. #oe or #ce should be toggled in each togg le bit status read. dq5 : exceed timing limits if the internal program/erase routine extends beyond the timi ng limits, dq5 will go high, indi cating program/erase failure. dq3 : block erase timer the status of the multi-block erase operation can be detected via the dq3 pin. dq3 will go high if 50 s of the block erase time window expires. in this case, the internal erase routine will initiate the erase operat ion.therefore, the device will not accept further write commands until the erase operation is completed. dq3 is low if the block erase time window is not expired. within the block erase time window , an additional block er ase command (30h) can be accepted. to confirm that the block eras e command has been accepted, the software ma y check the status of dq3 following each block erase com - mand. dq2 : toggle bit 2 the device generates a toggling pulse in dq 2 only if an internal erase routine or an erase/program suspend is in progress. when the device executes the internal erase routine, dq2 toggles if the bank including an erasing block is read. although the internal erase routine is in the exceeded time lim - its, dq2 toggles only if an erasing block in the exceeded time li mits is read. when the device is in the erase/program suspend mode, dq2 toggles only if an address in the erasing or programmi ng block is read. if a non-erasing or non-pr ogrammed block address is read during the erase/program suspend mode, then dq2 will produce valid data. dq2 will go high if the user tries to program a non-erase suspend block while the devic e is in the erase suspend mode. #oe or #ce should be toggled in each toggle bit status read. dq1 : buffer program abort indicator dq1 indocates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a "1". the system must issue the write-to-buffer- abort-reset command sequence to return the device to reading array data. rdy: ready normally the rdy signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. if rdy is low state, data is not valid at expected time, and if high state, data is valid. note th at, if ce is low and oe is high, the rdy is high state. - 24 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 figure 1. data polling algorithms figure 2. toggle bit algorithms start dq7 = data ? no dq5 = 1 ? fail pass yes dq7 = data ? no no yes read(dq0~dq7) valid address read(dq0~dq7) valid address start dq6 = toggle ? no dq5 = 1 ? fail pass no dq6 = toggle ? yes yes no read twice(dq0~dq7) valid address read(dq0~dq7) valid address yes yes read(dq0~dq7) valid address - 25 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 11.0 deep power down in order to reduce the power consumption of the device, it shall a deep power down mode inplemented on a separate pin. the deep power down mode is active when the deep power down signal is activated, high state. in deep power down the device shall turn off all circuitry in order to reach a power con - sumption of 2ua(typ). the device shall exit the deep power down mode within 75us after that the deep power down signal has been de-activated, set to low. in deep power down the state of the device chip select shal l have no impact on the device power consumption. all programmi ng capabilities of the device are inhibited. at the power up, the device shall accept any order of activation of the reset and deep power down signal. the device shall resp ond within the specified time for the signal that was deactivated/ac tivated latest. the deep power down mode is activated when dpd pin high state only. if dpd is asserted during a program or erase operation, the device requires a time of tdp (during internal routines) before the device is ready to enter dpd mode. note that user never float the dpd that is, dpd is always connected with v ih , v il .deep power down (dpd) note : not 100% tested. switching waveforms dpd timings not during internal routines dpd timings during internal routines figure 3. dpd timings parameter symbol all speed options unit min typ max dpd pin high (not duri ng internal routines) to dpd mode* tdp 100 - - ns dpd pin high (during internal routines) to dpd mode* tdp 20 - - s dpd low time before read* twkup 75 - - s t wkup ce , oe dpd t dp t wkup ce , oe t dp dpd - 26 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 12.0 common flash memory interface common flash memory interface is contrived to increase the compatibility of host system software. it provides the specific info rmation of the device, such as memory size and electrical f eatures. once this information has been obtained, the system software will know which command se ts to use to enable flash writes, block erases, and control the flash component. when the system writes the cfi command(98h) to address 55h, the de vice enters the cfi mode. and then if the system writes the a ddress shown in table 16 , the system can read the cfi data. query data are always presented on the lowest-order data outputs(dq0-7) only. in word(x16) mode, the upper data outputs(dq8-15) is 00h. to terminate this operation, the system must write the reset command. [table 16] common flash memory interface code description addresses (word mode) data query unique ascii string "qry" 10h 11h 12h 0051h 0052h 0059h primary oem command set 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = none exists) 17h 18h 0000h 0000h address for alternate oem extended table (00h = none exists) 19h 1ah 0000h 0000h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1bh 0017h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 0019h vpp (acceleration program) supply minimum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1dh 0085h vpp (acceleration program) supply maximum 00 = not supported, d7 - d4 : volt, d3 - d0 : 100mv 1eh 0095h typical timeout per single word write 2 n us 1fh 0007h typical timeout for max buffer write 2 n us(00h = not supported) 20h 000ah typical timeout per i ndividual block erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms(00h = not supported) 22h 0013h max. timeout for word write 2 n times typical 23h 0003h max. timeout for buffer write 2 n times typical 24h 0003h max. timeout per individual block erase 2 n times typical 25h 0003h max. timeout for full chip erase 2 n times typical(00h = not supported) 26h 0003h device size = 2 n byte 27h 001ah flash device interface description 28h 29h 0000h 0000h max. number of byte in multi-byte write = 2 n 2ah 2bh 000ah 0000h number of erase block regions within device (note 1) 2ch 0002h erase block region 1 information (boot block part : (k8a(10/11/12/13)15et(b)c) ) bits 0~15: y+1=block number bits 16~31: block size= z x 256bytes 2dh 2eh 2fh 30h 0003h 0000h 0080h 0000h - 27 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 note : 1) uniform block part (k8a(10/11/12/13)15ezc) : data is 01h boot block part (k8a(10/11/12/13)15et(b)c) : data is 02h 2) max. operating clock frequency : data is 85h in 108/133mhz part (k8a(11/13)15e(t/b/z)c), data is 53h in 66/83mhz part (k8a( 10/12)15e(t/b/z)c) description addresses (word mode) data erase block region 1 information (uniform block part : (k8a(10/11/12/13)15ezc) ) bits 0~15: y+1=block number bits 16~31: block size= z x 256bytes 2dh 2eh 2fh 30h 00ffh 0001h 0000h 0002h erase block region 2 information (boot block part : (k8a(10/11/12/13)15et(b)c) ) 31h 32h 33h 34h 00feh 0001h 0000h 0002h erase block region 2 information (uniform block part : (k8a(10/11/12/13)15ezc) ) 31h 32h 33h 34h 0000h 0000h 0000h 0000h erase block region 3 information 35h 36h 37h 38h 0000h 0000h 0000h 0000h erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string "pri" 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0031h address sensitive unlock (bits 1-0) 0 = required, 1= not required silcon revision number (bits 7-2) 45h 0000h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 46h 0002h block protect 00 = not supported, 01 = supported 47h 0001h block temporary unprotect 00 = not supported, 01 = supported 48h 0000h block protect/unprotect scheme 00 = not supported, 01 = supported 49h 0001h simultaneous operation 00 = not supported, 01 = supported 4ah 0001h burst mode type 00 = not supported, 01 = supported 4bh 0001h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page, 03 = 16 word page 4ch 0003h top/bottom boot/uniform block flag 02h = bottom boot device, 03h = top boot device, 04h = uniform device 4dh 0003h max. operating clock frequen cy (mhz ) (note 2) 4eh 0085h rww (read while write) functionality restrict ion (00h = non exists , 01h = exists) 4fh 0000h handshaking 00 = not supported at both mode, 01 = supported at sync. mode 10 = supported at async. mode, 11 = supported at both mode 50h 0001h - 28 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 13.0 absolute maximum ratings note : 1) minimum dc voltage is -0.5v on input/ output pins. during transitions, this level may fall to -2.0v for periods <20ns. maximum dc voltage is vcc+0.6v on input / output pins whic h, during transitions, may overshoot to vcc+2.0v for periods <20n s. 2) minimum dc input voltage is -0.5v on vpp . during transit ions, this level may fall to -2.0v for periods <20ns. maximum dc input voltage is +9.5v on vpp which, duri ng transitions, may overshoot to +12.0v for periods <20ns. 3) permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended period s may affect reliability. 14.0 recommended operating conditions (voltage reference to gnd) note : 1) data retention is not guaranteed on operatin g condition extended temperature(-25?c~85?c) over. parameter symbol rating unit voltage on any pin relative to vss v cc v cc -0.5 to +2.5 v v pp v in -0.5 to +9.5 all other pins -0.5 to +2.5 storage temperature t stg -65 to +100 c short circuit output current i os 5ma operating temperature t a (commercial temp.) 0 to +70 c t a (extended temp.) -25 to + 85 c parameter symbol min typ. max unit supply voltage v cc 1.7 1.8 1.95 v supply voltage v ss 000v - 29 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 15.0 dc characteristics note : 1) maximum i cc specifications are tested with v cc = v cc max. 2) i cc active while internal erase or internal program is in progress. 3) device enters automatic sleep mode when addresses are stable for t aa + 60ns. parameter symbol test conditions min typ max unit input leakage current i li v in =v ss to v cc , v cc =v cc max - 1.0 - + 1.0 a vpp leakage current i lip v cc =v cc max, v pp =v cc max - 1.0 - + 1.0 a v cc =v cc max, v pp =9.5v --35 a output leakage current i lo v out =v ss to v cc , v cc =v cc max, oe =v ih - 1.0 - + 1.0 a active burst read current i ccb1 ce =v il , oe =v ih (@133mhz) -3555ma active asynchronous read current i cc1 ce =v il , oe =v ih 10mhz - 35 55 ma active write current 2) i cc2 ce =v il , oe =v ih , we =v il , v pp =v ih -2540ma read while write current i cc3 ce =v il , oe =v ih -4570ma accelerated program current i cc4 ce =v il , oe =v ih , v pp =9.5v -2030ma standby current i cc5 ce = reset =v cc 0.2v - 30 120 a standby current during reset i cc6 reset = v ss 0.2v - 30 120 a automatic sleep mode 3) i cc7 ce =v ss 0.2v, other pins=v il or v ih v il = v ss 0.2v, v ih = v cc 0.2v - 30 120 a deep power down mode i cc8 -230 a input low voltage v il -0.5 - 0.4 v input high voltage v ih v cc -0.4 - v cc +0.4 v output low voltage v ol i ol = 100 a, v cc =v cc min --0.1v output high voltage v oh i oh = -100 a, v cc =v cc min v cc -0.1 --v voltage for accelerated program v id 8.5 9.0 9.5 v low vcc lock-out voltage v lko --1.4v vpp current in program/erase i vpp v pp = 9.5v -0.85ma v pp = 1.95v --50 a - 30 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 vcc power-up note : not 100% tested. switching waveforms figure 4. vcc power-up diagram parameter symbol all speed options unit min max vcc setup time t vcs 200 - s time between reset (high) and ce (low) t rh 200 - ns vcc/vccq reset ce t vcs t vccmin vih t rh dpd low - 31 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 16.0 capacitance (ta = 25 c, vcc = 1.8v, f = 1.0mhz) note : capacitance is periodica lly sampled and not 100% tested. 17.0 ac test condition item symbol test condition min max unit input capacitance c in v in =0v -10pf output capacitance c out v out =0v -10pf control pin capacitance c in2 v in =0v -10pf parameter value input pulse levels 0v to v cc input rise and fall times 3ns(max)@66mhz, 2.5ns (max)@83mhz, 1.5ns(max) @108mhz, 1ns(max)@133mhz input and output timing levels vcc/2 output load c l = 30pf address to address skew 3ns(max) 0v v cc v cc /2 v cc /2 input & output test point output load device under te s t * c l = 30pf including scope and jig capacitance input pulse and test point (including clk characterization) - 32 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 18.0 ac characteristics 18.1 synchronous/burst read parameter symbol 1c (66 mhz) 1d (83 mhz) 1e (108 mhz) 1f (133 mhz) unit min max min max min max min max initial access time t iaa - 95 - 95 - 95 - 95 ns burst access time valid clock to output delay t ba -11 - 9-7-6ns avd setup time to clk t avds 5 - 4 - 3.5 - 2.5 - ns avd hold time from clk t avdh 2- 2 -2-2-ns avd high to oe low t avdo 0- 0 -0-0-ns address setup time to clk t acs 5 - 4 - 3.5 - 2.5 - ns address hold time from clk t ach 6- 5 -2-2-ns data hold time from next clock cycle t bdh 3- 3 -2-2-ns output enable to rdy valid t oer -11 - 9-7-6ns ce disable to high z t cez -9 - 9-9-9ns oe disable to high z t oez -9 - 9-9-9ns ce setup time to clk t ces 6 - 4.5 - 4 - 3.5 - ns ce enable to rdy active t rdy -11 - 9-7-6ns clk to rdy setup time t rdya -11 - 9-7-6ns rdy setup time to clk t rdys 3- 3 -2-2-ns clk period t clk 15.1 - 12.05 - 9.26 - 7.52 - ns clk high or low time t clkh/l 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk 0.4x t clk 0.6x t clk ns clk fall or rise time t clkhcl - 3 - 2.5 - 1.5 - 1 ns - 33 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms figure 5. continuous burst mode read (133 mhz) figure 6. continuous burst mode read (108 mhz) t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z aa t rdys 7.5ns typ(133mhz). ce clk avd oe dq0: dq15 rdy a0-a24 13 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0, a11=1 da da+n da+1 da+2 da+3 da+4 da+5 da+6 1 2 3 4 5 11 12 13 t rdya t oer t rdy t avds t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z da da+1 da+2 da+n aa da+3 t rdys 9.25ns typ(108mhz). da+4 da+5 da+6 11 cycles for initial access shown. cr setting : a14=0, a13=1, a12=1, a11=1 ce clk avd oe dq0: dq15 rdy a0-a24 1 2 3 4 9 10 11 t rdya t oer t rdy t avds - 34 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms figure 7. 8 word linear burst mode with wrap around (133mhz) figure 8. 8 word linear burst with rdy set one cycle before data (wrap around mode, cr setting : a18=1) t ces t avds t avdh t acs t ach t iaa t ba t bdh hi-z aa t rdys 7.5ns typ(133mhz). ce clk avd oe dq0: dq15 rdy a0-a24 13 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0, a11=1 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 1 2 3 4 11 12 13 t rdya t oer t rdy t avds t ces t avds t avdh t acs t ach t iaa t ba t bdh hi-z aa t rdys 7.5ns typ(133mhz). ce clk avd oe dq0: dq15 rdy a0-a24 13 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0, a11=1 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 t rdya 1 2 3 4 111 12 10 13 t oer t rdy t avds - 35 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms figure 9. 16 word linear burst mode with wrap around (133mhz) 18.2 asynchronous read note: not 100% tested. parameter symbol all speed option unit min max access time from ce low t ce - 100 ns asynchronous access time t aa - 100 ns page address access time t pa -15ns output hold time from address, ce or oe t oh 3-ns avd low setup time to ce enable t avdcs 0-ns avd low hold time from ce enable t avdch 0-ns output enable to output valid t oe -15ns output enable hold time read t oeh 0-ns toggle and data polling 10 - ns output disable to high z* t oez -9ns t ces t avds t avdh t acs t ach t iaa t ba t bdh t cez t oez hi-z hi-z hi-z aa t rdys 7.5ns typ(133mhz). ce clk avd oe dq0: dq15 rdy a0-a24 13 cycles for initial access shown. cr setting : a14=1, a13=0, a12=0, a11=1 d7 d6 d8 d9 d10 d15 d0 1 2 3 4 11 12 13 5 t rdya t oer t rdy t avds - 36 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms asynchronous mode read figure 10. asynchronous mode read note : 1) va=valid read address, rd=read data. 2) avd should be held vil in asynchronous read mode. 3) asynchronous mode may not support read following four sequential invalid read condition within 200ns. 4) clk "high" should be prohibited in as ynchronous read mode start (from ce low). t oe va valid rd t ce t oeh t oez ce oe we dq0-dq15 a0-a24 t aa clk v il avd t avdcs t avdch - 37 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms page read operations figure 11. asynchronous page mode read note : clk "high" should be prohibited in asynchronous read mode start (from ce low). t oe va t ce t oeh t oez ce oe we dq0-dq15 a4-a24 t aa clk v il avd t avdcs t avdch a0-a3 aa ab ac da db dp ap t pa t oh - 38 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 hardware reset ( reset ) note : 1) not 100% tested. switching waveforms reset timings not during internal routines reset timings during internal routines figure 12. reset timings parameter symbol all speed options unit min max reset pin low(during internal routines) to read mode 1) t ready -20 s reset pin low(not during internal routines) to read mode 1) t ready - 500 ns reset pulse width* t rp 200 - ns reset high time before read 1) t rh 200 - ns t rh ce , oe reset t rp t ready t ready ce , oe reset t rp - 39 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 18.3 erase/program operation note : 1) not 100% tested. 2) internal programming algorithm is optimized for buffer program, so normal word programming or single word buffer program use buffer program algorithm. 3) typical 512-word buffer program time pays due regard to that each program data pattern ("11", "10". "01", "00") has a same p ortion in 512-word buffer. parameter symbol all speed option unit min typ max we cycle time 1) t wc 75 - - ns address setup time t as 0- -ns address hold time t ah 30 - - ns data setup time t ds 30 - - ns data hold time t dh 0- -ns read recovery time before write t ghwl 0- -ns ce setup time t cs 0- -ns ce hold time t ch 0- -ns we pulse width t wp 30 - - ns we pulse width high t wph 45 - - ns latency between read and write operations t sr/w 0- -ns word programming operation 2) t pgm -80- s single word buffer program 2) t pgm_bp - 250 - s 512-word buffer program 3) t pgm_bp - 716.8 - s accelerated programming operation t accpgm -80- s accelerated single word buffer program t accpgm_bp -0.7- s accelerated 512-word buffer program 3) t accpgm_bp - 358.4 - s block erase operation (64kw block) t bers -0.6-sec vpp rise and fall time t vpp 500 - - ns vpp setup time (during accelerated programming) t vps 1- - s - 40 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 18.4 erase/program performance note : 1) 25 c, vcc = 1.8v, 100,000 cycles, typical pattern. 2) system-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. 3) chip erase time & accel. chip erase time for boot block part : k8a(10/11/12/13)15et(b)c 4) accelerated program/erase cycling must be limited below 100cycl es for optimum performance. am bient temperature requirements : ta = 30 c10 c switching waveforms program operations note : 1) pa = program address, pd = program data, va = valid address for reading status bits. 2) ?in progress? and ?complete? refer to status of program operation. 3) a16?a24 are don?t care during command sequence unlock cycles. 4) status reads in this figure is asynchronous read , but status read in synchr onous mode is also supported. figure 13. program operation timing parameter limits unit comments min. typ. max. block erase time 64 kword - 0.6 3.0 sec includes 00h programming prior to erasure 16 kword - 0.3 1.5 chip erase time 3) - 307.8 1539 accelerated block erase time 4) 64 kword - 0.4 3.0 16 kword - 0.2 1.5 accelerated chip erase time 3),4) - 205.2 1026 word programming time - 80 550 s / word excludes system level over- head 512-word buffer programming time - 1.4 7 accelerated word programming time - 80 550 accelerated 512-word buffer programming time - 0.7 3.5 chip buffer programming time - 46.9 234.5 sec excludes system level over- head accelerated buffer chip programming time - 23.4 117 program command sequence (last two cycles) a0:a24 we ce clk t ah t ds t dh t ch t wp t cs t wph t wc t pgm pa va va in progress complete pd a0h 555h dq0-dq15 oe v cc read status data v il t as - 41 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms buffer program operations note : 1) ba = block address, wc = word count, pa = program address, pd = program data, va = valid address for reading status bits. 2) sequential pa_1, pa_2, ... , pa_n must have same address bits a24(max.) ~ a9 as pa_0 entered firstly 3) the number of program/data pairs enter ed must be same as wc+1 because wc = n. 4) ?in progress? and ?complete? refer to status of program operation. 5) a16?a24 are don?t care during command sequence unlock cycles. 6) status reads in this figure is asynchronous read , but status read in synchr onous mode is also supported. figure 14. buffer program operation timing a0:a24 we ce clk t as t ah t ds t wp t cs t wph t wc aah dq0: dq15 oe v cc v il 55h 25h wc pd_0 pd_1 pd_n 29h ba ba pa_0 pa_1 pa_n ba t pgm_bp buffer program command sequence word count program address/data pairs (wc+1) "buffer to flash" 555h 2aah - 42 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms erase operation note : 1) ba is the block address for block erase. 2) address bits a16?a24 are don?t cares during unlock cycles in the command sequence. 3) status reads in this figure is asynchronous read , but status read in synchr onous mode is also supported. figure 15. chlp/block erase operations erase command sequence (last two cycles) a0:a24 we ce t ds t dh t ch t bers ba va va in progress complete 30h 55h 2aah dq0-dq15 oe v cc read status data 555h for chip erase 10h for chip erase t wp t cs t wph t wc clk v il t ah t as - 43 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms unlock bypass program operations (accelerated program) unlock bypass block erase operations note : 1) vpp can be left high for subsequent programming pulses. 2) use setup and hold times from conventional program operations. 3) conventional program/erase commands as well as unlock bypass program/erase commands can be used when the vid is applied to vpp. figure 16. unlock bypass operation timings ce oe a0:a24 v pp we dq0: dq15 t vps v il or v ih v id t vpp pa don?t care a0h pd don?t care don?t care ce oe a0:a24 v pp we dq0: dq15 t vps v il or v ih v id t vpp ba don?t care 80h 30h don?t care 555h for chip erase 10h for chip erase don?t care - 44 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms data polling operations note : 1) va = valid address. when the internal routine operation is complete, and data polling will output true data. figure 17. data polling timings (during internal routine) toggle bit operations note : 1) va = valid address. when the internal routine operation is complete, the toggle bits will stop toggling. figure 18. toggle bit timings (during internal routine) t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe dq0: dq15 rdy va a0-a24 t rdys status data va status data t ces t avds t avdh t acs t ach t iaa hi-z ce clk avd oe dq0: dq15 rdy va a0-a24 t rdys status data va status data - 45 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 switching waveforms read while write operations figure 19. read while write operation note : breakpoints in waveforms indicate that system may alternately read array data from the ?non-busy bank? and checking the status of the program or erase operation in the ?busy? bank. t wc ce oe we dq0: avd dq15 a0-a24 pd/30h aah pa/ba ra ra rd rd last cycle in program or block erase command sequence read status in same bank and/or array data from other bank t rc t rc t wc t oe t oeh t wph t wp t aa t oeh t ds t dh t sr/w t as t ah t ghwl command sequences program or erase begin another 555h - 46 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 19.0 crossing of first word boundary in burst read mode the additional clock insertion for word boundary is needed only at the first crossing of word boundary. this means that no addi tional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. also, the number of additional clock cycle for the first w ord boundary can varies from zero to thirteen cycles, and the exact number of additio nal clock cycle depends on the star ting address of burst read and programmable wait state settings. for example, if the starting address is 16n+15 (the worst case) and programmable wait state setting(a<14:11>) is "0011" (which means data is valid on the 7th active clk edge after avd transition to vih), six addi tional clock cycle is needed. similarly, if the starting address is 16n+15 (the worst case) a nd programmable wait state setting(a<14:11>) is "0010" (which me ans data is valid on the 6th active clk edge after avd transition to vih), five additional clock cycle is needed. below table shows the starting address vs. addi tional clock cycles for first word boundary. starting address vs. additional clock cycles for first word boundary note : address bit a<14:11> means the programmable wait state on burst mode configuration register. refer to ta b l e 10 . srarting address group for burst read the residue of (address/16) lsb bits of address additional clock cycles for first word boundary (note1) a<14:11> "0000" valid data : 4th clk a<14:11> "0001" valid data : 5th clk a<14:11> "0010" valid data : 6th clk ... a<14:11> "1010" valid data : 14th clk 16n 0 0000 0 cycle 0 cycle 0 cycle ... 0 cycle 16n+1 1 0001 0 cycle 0 cycle 0 cycle ... 0 cycle 16n+2 2 0010 0 cycle 0 cycle 0 cycle ... 0 cycle 16n+3 3 0011 0 cycle 0 cycle 0 cycle ... 1 cycle 16n+4 4 0100 0 cycle 0 cycle 0 cycle ... 2 cycle 16n+5 5 0101 0 cycle 0 cycle 0 cycle ... 3 cycle 16n+6 6 0110 0 cycle 0 cycle 0 cycle ... 4 cycle 16n+7 7 0111 0 cycle 0 cycle 0 cycle ... 5 cycle 16n+8 8 1000 0 cycle 0 cycle 0 cycle ... 6 cycle 16n+9 9 1001 0 cycle 0 cycle 0 cycle ... 7 cycle 16n+10 10 1010 0 cycle 0 cycle 0 cycle ... 8 cycle 16n+11 11 1011 0 cycle 0 cycle 1 cycle ... 9 cycle 16n+12 12 1100 0 cycle 1 cycle 2 cycle ... 10 cycle 16n+13 13 1101 1 cycle 2 cycle 3 cycle ... 11 cycle 16n+14 14 1110 2 cycle 3 cycle 4 cycle ... 12 cycle 16n+15 15 1111 3 cycle 4 cycle 5 cycle ... 13 cycle - 47 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 case 1 : start from "16n" address group note : 1) address boundary occurs every 16 words beginning at address 000000fh, 000001fh, 000002fh, etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 20. crossing of first word boundary in burst read mode. case 2 : start from "16n+3" address group note : 1) address boundary occurs every 16 words be ginning at address 000000fh, 000001fh, 000002fh, etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 21. crossing of first word boundary in burst read mode. 14th rising edge clk cr setting : a14=1, a13=0, a12=1, a11=0 ce oe rdy clk data bus : avd t cez t oez t oer 00 0c 10 11 12 13 no additional cycle for first word boundary 0d 0e 0f 0b a0-a24 0c 10 11 12 0f 0b 0d 0e aa ce oe rdy clk avd t cez t oez t oer 00 0e 12 13 14 additional 1 cycle for first word boundary 0f 10 14th rising edge clk cr setting : a14=1, a13=0, a12=1, a11=0 0d data bus : a0-a24 0e 11 12 13 10 0d aa 0f 11 - 48 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 case3 : start from "16n+4" address group case 4 : start from "16n+15" address group note : 1) address boundary occurs every 16 words beginning at address 000000fh, 000001fh, 000002fh, etc. 2) address 000000h is also a boundary crossing. 3) no additional clock cycles are needed except for 1st boundary crossing. figure 22. crossing of first word boundary in burst read mode. ce oe rdy clk avd t cez t oez t oer 00 0f 11 12 13 14 additional 2 cycle for first word boundary 10 14th rising edge clk cr setting : a14=1, a13=0, a12=1, a11=0 0e data bus : a0-a24 11 12 13 10 0e aa 0f ce oe rdy clk avd t oer 00 10 11 additional 13 cycle for first word boundary 14th rising edge clk cr setting : a14=1, a13=0, a12=1, a11=0 data bus : a0-a24 10 11 12 aa 3f 3f - 49 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 17] top boot block address table bank block block size (x16) address range bank 0 ba514 16 kwords 1ffc000h-1ffffffh ba513 16 kwords 1ff8000h-1ffbfffh ba512 16 kwords 1ff4000h-1ff7fffh ba511 16 kwords 1ff0000h-1ff3fffh ba510 64 kwords 1fe0000h-1feffffh ba509 64 kwords 1fd0000h-1fdffffh ba508 64 kwords 1fc0000h-1fcffffh ba507 64 kwords 1fb0000h-1fbffffh ba506 64 kwords 1fa0000h-1faffffh ba505 64 kwords 1f90000h-1f9ffffh ba504 64 kwords 1f80000h-1f8ffffh ba503 64 kwords 1f70000h-1f7ffffh ba502 64 kwords 1f60000h-1f6ffffh ba501 64 kwords 1f50000h-1f5ffffh ba500 64 kwords 1f40000h-1f4ffffh ba499 64 kwords 1f30000h-1f3ffffh ba498 64 kwords 1f20000h-1f2ffffh ba497 64 kwords 1f10000h-1f1ffffh ba496 64 kwords 1f00000h-1f0ffffh ba495 64 kwords 1ef0000h-1efffffh ba494 64 kwords 1ee0000h-1eeffffh ba493 64 kwords 1ed0000h-1edffffh ba492 64 kwords 1ec0000h-1ecffffh ba491 64 kwords 1eb0000h-1ebffffh ba490 64 kwords 1ea0000h-1eaffffh ba489 64 kwords 1e90000h-1e9ffffh ba488 64 kwords 1e80000h-1e8ffffh ba487 64 kwords 1e70000h-1e7ffffh ba486 64 kwords 1e60000h-1e6ffffh ba485 64 kwords 1e50000h-1e5ffffh ba484 64 kwords 1e40000h-1e4ffffh ba483 64 kwords 1e30000h-1e3ffffh ba482 64 kwords 1e20000h-1e2ffffh ba481 64 kwords 1e10000h-1e1ffffh ba480 64 kwords 1e00000h-1e0ffffh bank 1 ba479 64 kwords 1df0000h-1dfffffh ba478 64 kwords 1de0000h-1deffffh ba477 64 kwords 1dd0000h-1ddffffh ba476 64 kwords 1dc0000h-1dcffffh ba475 64 kwords 1db0000h-1dbffffh ba474 64 kwords 1da0000h-1daffffh ba473 64 kwords 1d90000h-1d9ffffh ba472 64 kwords 1d80000h-1d8ffffh ba471 64 kwords 1d70000h-1d7ffffh ba470 64 kwords 1d60000h-1d6ffffh - 50 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 1 ba469 64 kwords 1d50000h-1d5ffffh ba468 64 kwords 1d40000h-1d4ffffh ba467 64 kwords 1d30000h-1d3ffffh ba466 64 kwords 1d20000h-1d2ffffh ba465 64 kwords 1d10000h-1d1ffffh ba464 64 kwords 1d00000h-1d0ffffh ba463 64 kwords 1cf0000h-1cfffffh ba462 64 kwords 1ce0000h-1ceffffh ba461 64 kwords 1cd0000h-1cdffffh ba460 64 kwords 1cc0000h-1ccffffh ba459 64 kwords 1cb0000h-1cbffffh ba458 64 kwords 1ca0000h-1caffffh ba457 64 kwords 1c90000h-1c9ffffh ba456 64 kwords 1c80000h-1c8ffffh ba455 64 kwords 1c70000h-1c7ffffh ba454 64 kwords 1c60000h-1c6ffffh ba453 64 kwords 1c50000h-1c5ffffh ba452 64 kwords 1c40000h-1c4ffffh ba451 64 kwords 1c30000h-1c3ffffh ba450 64 kwords 1c20000h-1c2ffffh ba449 64 kwords 1c10000h-1c1ffffh ba448 64 kwords 1c00000h-1c0ffffh bank 2 ba447 64 kwords 1bf0000h-1bfffffh ba446 64 kwords 1be0000h-1beffffh ba445 64 kwords 1bd0000h-1bdffffh ba444 64 kwords 1bc0000h-1bcffffh ba443 64 kwords 1bb0000h-1bbffffh ba442 64 kwords 1ba0000h-1baffffh ba441 64 kwords 1b90000h-1b9ffffh ba440 64 kwords 1b80000h-1b8ffffh ba439 64 kwords 1b70000h-1b7ffffh ba438 64 kwords 1b60000h-1b6ffffh ba437 64 kwords 1b50000h-1b5ffffh ba436 64 kwords 1b40000h-1b4ffffh ba435 64 kwords 1b30000h-1b3ffffh ba434 64 kwords 1b20000h-1b2ffffh ba433 64 kwords 1b10000h-1b1ffffh ba432 64 kwords 1b00000h-1b0ffffh ba431 64 kwords 1af0000h-1afffffh ba430 64 kwords 1ae0000h-1aeffffh ba429 64 kwords 1ad0000h-1adffffh ba428 64 kwords 1ac0000h-1acffffh ba427 64 kwords 1ab0000h-1abffffh ba426 64 kwords 1aa0000h-1aaffffh ba425 64 kwords 1a90000h-1a9ffffh - 51 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 2 ba424 64 kwords 1a80000h-1a8ffffh ba423 64 kwords 1a70000h-1a7ffffh ba422 64 kwords 1a60000h-1a6ffffh ba421 64 kwords 1a50000h-1a5ffffh ba420 64 kwords 1a40000h-1a4ffffh ba419 64 kwords 1a30000h-1a3ffffh ba418 64 kwords 1a20000h-1a2ffffh ba417 64 kwords 1a10000h-1a1ffffh ba416 64 kwords 1a00000h-1a0ffffh bank 3 ba415 64 kwords 19f0000h-19fffffh ba414 64 kwords 19e0000h-19effffh ba413 64 kwords 19d0000h-19dffffh ba412 64 kwords 19c0000h-19cffffh ba411 64 kwords 19b0000h-19bffffh ba410 64 kwords 19a0000h-19affffh ba409 64 kwords 1990000h-199ffffh ba408 64 kwords 1980000h-198ffffh ba407 64 kwords 1970000h-197ffffh ba406 64 kwords 1960000h-196ffffh ba405 64 kwords 1950000h-195ffffh ba404 64 kwords 1940000h-194ffffh ba403 64 kwords 1930000h-193ffffh ba402 64 kwords 1920000h-192ffffh ba401 64 kwords 1910000h-191ffffh ba400 64 kwords 1900000h-190ffffh ba399 64 kwords 18f0000h-18fffffh ba398 64 kwords 18e0000h-18effffh ba397 64 kwords 18d0000h-18dffffh ba396 64 kwords 18c0000h-18cffffh ba395 64 kwords 18b0000h-18bffffh ba394 64 kwords 18a0000h-18affffh ba393 64 kwords 1890000h-189ffffh ba392 64 kwords 1880000h-188ffffh ba391 64 kwords 1870000h-187ffffh ba390 64 kwords 1860000h-186ffffh ba389 64 kwords 1850000h-185ffffh ba388 64 kwords 1840000h-184ffffh ba387 64 kwords 1830000h-183ffffh ba386 64 kwords 1820000h-182ffffh ba385 64 kwords 1810000h-181ffffh ba384 64 kwords 1800000h-180ffffh bank 4 ba383 64 kwords 17f0000h-17fffffh ba382 64 kwords 17e0000h-17effffh ba381 64 kwords 17d0000h-17dffffh ba380 64 kwords 17c0000h-17cffffh - 52 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 4 ba379 64 kwords 17b0000h-17bffffh ba378 64 kwords 17a0000h-17affffh ba377 64 kwords 1790000h-179ffffh ba376 64 kwords 1780000h-178ffffh ba375 64 kwords 1770000h-177ffffh ba374 64 kwords 1760000h-176ffffh ba373 64 kwords 1750000h-175ffffh ba372 64 kwords 1740000h-174ffffh ba371 64 kwords 1730000h-173ffffh ba370 64 kwords 1720000h-172ffffh ba369 64 kwords 1710000h-171ffffh ba368 64 kwords 1700000h-170ffffh ba367 64 kwords 16f0000h-16fffffh ba366 64 kwords 16e0000h-16effffh ba365 64 kwords 16d0000h-16dffffh ba364 64 kwords 16c0000h-16cffffh ba363 64 kwords 16b0000h-16bffffh ba362 64 kwords 16a0000h-16affffh ba361 64 kwords 1690000h-169ffffh ba360 64 kwords 1680000h-168ffffh ba359 64 kwords 1670000h-167ffffh ba358 64 kwords 1660000h-166ffffh ba357 64 kwords 1650000h-165ffffh ba356 64 kwords 1640000h-164ffffh ba355 64 kwords 1630000h-163ffffh ba354 64 kwords 1620000h-162ffffh ba353 64 kwords 1610000h-161ffffh ba352 64 kwords 1600000h-160ffffh bank5 ba351 64 kwords 15f0000h-15fffffh ba350 64 kwords 15e0000h-15effffh ba349 64 kwords 15d0000h-15dffffh ba348 64 kwords 15c0000h-15cffffh ba347 64 kwords 15b0000h-15bffffh ba346 64 kwords 15a0000h-15affffh ba345 64 kwords 1590000h-159ffffh ba344 64 kwords 1580000h-158ffffh ba343 64 kwords 1570000h-157ffffh ba342 64 kwords 1560000h-156ffffh ba341 64 kwords 1550000h-155ffffh ba340 64 kwords 1540000h-154ffffh ba339 64 kwords 1530000h-153ffffh ba338 64 kwords 1520000h-152ffffh ba337 64 kwords 1510000h-151ffffh ba336 64 kwords 1500000h-150ffffh - 53 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 5 ba335 64 kwords 14f0000h-14fffffh ba334 64 kwords 14e0000h-14effffh ba333 64 kwords 14d0000h-14dffffh ba332 64 kwords 14c0000h-14cffffh ba331 64 kwords 14b0000h-14bffffh ba330 64 kwords 14a0000h-14affffh ba329 64 kwords 1490000h-149ffffh ba328 64 kwords 1480000h-148ffffh ba327 64 kwords 1470000h-147ffffh ba326 64 kwords 1460000h-146ffffh ba325 64 kwords 1450000h-145ffffh ba324 64 kwords 1440000h-144ffffh ba323 64 kwords 1430000h-143ffffh ba322 64 kwords 1420000h-142ffffh ba321 64 kwords 1410000h-141ffffh ba320 64 kwords 1400000h-140ffffh bank 6 ba319 64 kwords 13f0000h-13fffffh ba318 64 kwords 13e0000h-13effffh ba317 64 kwords 13d0000h-13dffffh ba316 64 kwords 13c0000h-13cffffh ba315 64 kwords 13b0000h-13bffffh ba314 64 kwords 13a0000h-13affffh ba313 64 kwords 1390000h-139ffffh ba312 64 kwords 1380000h-138ffffh ba311 64 kwords 1370000h-137ffffh ba310 64 kwords 1360000h-136ffffh ba309 64 kwords 1350000h-135ffffh ba308 64 kwords 1340000h-134ffffh ba307 64 kwords 1330000h-133ffffh ba306 64 kwords 1320000h-132ffffh ba305 64 kwords 1310000h-131ffffh ba304 64 kwords 1300000h-130ffffh ba303 64 kwords 12f0000h-12fffffh ba302 64 kwords 12e0000h-12effffh ba301 64 kwords 12d0000h-12dffffh ba300 64 kwords 12c0000h-12cffffh ba299 64 kwords 12b0000h-12bffffh ba298 64 kwords 12a0000h-12affffh ba297 64 kwords 1290000h-129ffffh ba296 64 kwords 1280000h-128ffffh ba295 64 kwords 1270000h-127ffffh ba294 64 kwords 1260000h-126ffffh ba293 64 kwords 1250000h-125ffffh ba292 64 kwords 1240000h-124ffffh ba291 64 kwords 1230000h-123ffffh - 54 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 6 ba290 64 kwords 1220000h-122ffffh ba289 64 kwords 1210000h-121ffffh ba288 64 kwords 1200000h-120ffffh bank 7 ba287 64 kwords 11f0000h-11fffffh ba286 64 kwords 11e0000h-11effffh ba285 64 kwords 11d0000h-11dffffh ba284 64 kwords 11c0000h-11cffffh ba283 64 kwords 11b0000h-11bffffh ba282 64 kwords 11a0000h-11affffh ba281 64 kwords 1190000h-119ffffh ba280 64 kwords 1180000h-118ffffh ba279 64 kwords 1170000h-117ffffh ba278 64 kwords 1160000h-116ffffh ba277 64 kwords 1150000h-115ffffh ba276 64 kwords 1140000h-114ffffh ba275 64 kwords 1130000h-113ffffh ba274 64 kwords 1120000h-112ffffh ba273 64 kwords 1110000h-111ffffh ba272 64 kwords 1100000h-110ffffh ba271 64 kwords 10f0000h-10fffffh ba270 64 kwords 10e0000h-10effffh ba269 64 kwords 10d0000h-10dffffh ba268 64 kwords 10c0000h-10cffffh ba267 64 kwords 10b0000h-10bffffh ba266 64 kwords 10a0000h-10affffh ba265 64 kwords 1090000h-109ffffh ba264 64 kwords 1080000h-108ffffh ba263 64 kwords 1070000h-107ffffh ba262 64 kwords 1060000h-106ffffh ba261 64 kwords 1050000h-105ffffh ba260 64 kwords 1040000h-104ffffh ba259 64 kwords 1030000h-103ffffh - 55 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 7 ba258 64 kwords 1020000h-102ffffh ba257 64 kwords 1010000h-101ffffh ba256 64 kwords 1000000h-100ffffh bank 8 ba255 64 kwords 0ff0000h-0ffffffh ba254 64 kwords 0fe0000h-0feffffh ba253 64 kwords 0fd0000h-0fdffffh ba252 64 kwords 0fc0000h-0fcffffh ba251 64 kwords 0fb0000h-0fbffffh ba250 64 kwords 0fa0000h-0faffffh ba249 64 kwords 0f90000h-0f9ffffh ba248 64 kwords 0f80000h-0f8ffffh ba247 64 kwords 0f70000h-0f7ffffh ba246 64 kwords 0f60000h-0f6ffffh ba245 64 kwords 0f50000h-0f5ffffh ba244 64 kwords 0f40000h-0f4ffffh ba243 64 kwords 0f30000h-0f3ffffh ba242 64 kwords 0f20000h-0f2ffffh ba241 64 kwords 0f10000h-0f1ffffh ba240 64 kwords 0f00000h-0f0ffffh ba239 64 kwords 0ef0000h-0efffffh ba238 64 kwords 0ee0000h-0eeffffh ba237 64 kwords 0ed0000h-0edffffh ba236 64 kwords 0ec0000h-0ecffffh ba235 64 kwords 0eb0000h-0ebffffh ba234 64 kwords 0ea0000h-0eaffffh ba233 64 kwords 0e90000h-0e9ffffh ba232 64 kwords 0e80000h-0e8ffffh ba231 64 kwords 0e70000h-0e7ffffh ba230 64 kwords 0e60000h-0e6ffffh ba229 64 kwords 0e50000h-0e5ffffh ba228 64 kwords 0e40000h-0e4ffffh ba227 64 kwords 0e30000h-0e3ffffh ba226 64 kwords 0e20000h-0e2ffffh ba225 64 kwords 0e10000h-0e1ffffh ba224 64 kwords 0e00000h-0e0ffffh bank 9 ba223 64 kwords 0df0000h-0dfffffh ba222 64 kwords 0de0000h-0deffffh ba221 64 kwords 0dd0000h-0ddffffh ba220 64 kwords 0dc0000h-0dcffffh ba219 64 kwords 0db0000h-0dbffffh ba218 64 kwords 0da0000h-0daffffh ba217 64 kwords 0d90000h-0d9ffffh ba216 64 kwords 0d80000h-0d8ffffh ba215 64 kwords 0d70000h-0d7ffffh ba214 64 kwords 0d60000h-0d6ffffh - 56 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 9 ba213 64 kwords 0d50000h-0d5ffffh ba212 64 kwords 0d40000h-0d4ffffh ba211 64 kwords 0d30000h-0d3ffffh ba210 64 kwords 0d20000h-0d2ffffh ba209 64 kwords 0d10000h-0d1ffffh ba208 64 kwords 0d00000h-0d0ffffh ba207 64 kwords 0cf0000h-0cfffffh ba206 64 kwords 0ce0000h-0ceffffh ba205 64 kwords 0cd0000h-0cdffffh ba204 64 kwords 0cc0000h-0ccffffh ba203 64 kwords 0cb0000h-0cbffffh ba202 64 kwords 0ca0000h-0caffffh ba201 64 kwords 0c90000h-0c9ffffh ba200 64 kwords 0c80000h-0c8ffffh ba199 64 kwords 0c70000h-0c7ffffh ba198 64 kwords 0c60000h-0c6ffffh ba197 64 kwords 0c50000h-0c5ffffh ba196 64 kwords 0c40000h-0c4ffffh ba195 64 kwords 0c30000h-0c3ffffh ba194 64 kwords 0c20000h-0c2ffffh ba193 64 kwords 0c10000h-0c1ffffh ba192 64 kwords 0c00000h-0c0ffffh bank 10 ba191 64 kwords 0bf0000h-0bfffffh ba190 64 kwords 0be0000h-0beffffh ba189 64 kwords 0bd0000h-0bdffffh ba188 64 kwords 0bc0000h-0bcffffh ba187 64 kwords 0bb0000h-0bbffffh ba186 64 kwords 0ba0000h-0baffffh ba185 64 kwords 0b90000h-0b9ffffh ba184 64 kwords 0b80000h-0b8ffffh ba183 64 kwords 0b70000h-0b7ffffh ba182 64 kwords 0b60000h-0b6ffffh ba181 64 kwords 0b50000h-0b5ffffh ba180 64 kwords 0b40000h-0b4ffffh ba179 64 kwords 0b30000h-0b3ffffh ba178 64 kwords 0b20000h-0b2ffffh ba177 64 kwords 0b10000h-0b1ffffh ba176 64 kwords 0b00000h-0b0ffffh ba175 64 kwords 0af0000h-0afffffh ba174 64 kwords 0ae0000h-0aeffffh ba173 64 kwords 0ad0000h-0adffffh ba172 64 kwords 0ac0000h-0acffffh ba171 64 kwords 0ab0000h-0abffffh ba170 64 kwords 0aa0000h-0aaffffh ba169 64 kwords 0a90000h-0a9ffffh - 57 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 10 ba168 64 kwords 0a80000h-0a8ffffh ba167 64 kwords 0a70000h-0a7ffffh ba166 64 kwords 0a60000h-0a6ffffh ba165 64 kwords 0a50000h-0a5ffffh ba164 64 kwords 0a40000h-0a4ffffh ba163 64 kwords 0a30000h-0a3ffffh ba162 64 kwords 0a20000h-0a2ffffh ba161 64 kwords 0a10000h-0a1ffffh ba160 64 kwords 0a00000h-0a0ffffh bank 11 ba159 64 kwords 09f0000h-09fffffh ba158 64 kwords 09e0000h-09effffh ba157 64 kwords 09d0000h-09dffffh ba156 64 kwords 09c0000h-09cffffh ba155 64 kwords 09b0000h-09bffffh ba154 64 kwords 09a0000h-09affffh ba153 64 kwords 0990000h-099ffffh ba152 64 kwords 0980000h-098ffffh ba151 64 kwords 0970000h-097ffffh ba150 64 kwords 0960000h-096ffffh ba149 64 kwords 0950000h-095ffffh ba148 64 kwords 0940000h-094ffffh ba147 64 kwords 0930000h-093ffffh ba146 64 kwords 0920000h-092ffffh ba145 64 kwords 0910000h-091ffffh ba144 64 kwords 0900000h-090ffffh ba143 64 kwords 08f0000h-08fffffh ba142 64 kwords 08e0000h-08effffh ba141 64 kwords 08d0000h-08dffffh ba140 64 kwords 08c0000h-08cffffh ba139 64 kwords 08b0000h-08bffffh ba138 64 kwords 08a0000h-08affffh ba137 64 kwords 0890000h-089ffffh ba136 64 kwords 0880000h-088ffffh ba135 64 kwords 0870000h-087ffffh ba134 64 kwords 0860000h-086ffffh ba133 64 kwords 0850000h-085ffffh ba132 64 kwords 0840000h-084ffffh ba131 64 kwords 0830000h-083ffffh ba130 64 kwords 0820000h-082ffffh ba129 64 kwords 0810000h-081ffffh ba128 64 kwords 0800000h-080ffffh bank 12 ba127 64 kwords 07f0000h-07fffffh ba126 64 kwords 07e0000h-07effffh ba125 64 kwords 07d0000h-07dffffh ba124 64 kwords 07c0000h-07cffffh - 58 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 12 ba123 64 kwords 07b0000h-07bffffh ba122 64 kwords 07a0000h-07affffh ba121 64 kwords 0790000h-079ffffh ba120 64 kwords 0780000h-078ffffh ba119 64 kwords 0770000h-077ffffh ba118 64 kwords 0760000h-076ffffh ba117 64 kwords 0750000h-075ffffh ba116 64 kwords 0740000h-074ffffh ba115 64 kwords 0730000h-073ffffh ba114 64 kwords 0720000h-072ffffh ba113 64 kwords 0710000h-071ffffh ba112 64 kwords 0700000h-070ffffh ba111 64 kwords 06f0000h-06fffffh ba110 64 kwords 06e0000h-06effffh ba109 64 kwords 06d0000h-06dffffh ba108 64 kwords 06c0000h-06cffffh ba107 64 kwords 06b0000h-06bffffh ba106 64 kwords 06a0000h-06affffh ba105 64 kwords 0690000h-069ffffh ba104 64 kwords 0680000h-068ffffh ba103 64 kwords 0670000h-067ffffh ba102 64 kwords 0660000h-066ffffh ba101 64 kwords 0650000h-065ffffh ba100 64 kwords 0640000h-064ffffh ba99 64 kwords 0630000h-063ffffh ba98 64 kwords 0620000h-062ffffh ba97 64 kwords 0610000h-061ffffh ba96 64 kwords 0600000h-060ffffh bank13 ba95 64 kwords 05f0000h-05fffffh ba94 64 kwords 05e0000h-05effffh ba93 64 kwords 05d0000h-05dffffh ba92 64 kwords 05c0000h-05cffffh ba91 64 kwords 05b0000h-05bffffh ba90 64 kwords 05a0000h-05affffh ba89 64 kwords 0590000h-059ffffh ba88 64 kwords 0580000h-058ffffh ba87 64 kwords 0570000h-057ffffh ba86 64 kwords 0560000h-056ffffh ba85 64 kwords 0550000h-055ffffh ba84 64 kwords 0540000h-054ffffh ba83 64 kwords 0530000h-053ffffh ba82 64 kwords 0520000h-052ffffh ba81 64 kwords 0510000h-051ffffh ba80 64 kwords 0500000h-050ffffh - 59 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 13 ba79 64 kwords 04f0000h-04fffffh ba78 64 kwords 04e0000h-04effffh ba77 64 kwords 04d0000h-04dffffh ba76 64 kwords 04c0000h-04cffffh ba75 64 kwords 04b0000h-04bffffh ba74 64 kwords 04a0000h-04affffh ba73 64 kwords 0490000h-049ffffh ba72 64 kwords 0480000h-048ffffh ba71 64 kwords 0470000h-047ffffh ba70 64 kwords 0460000h-046ffffh ba69 64 kwords 0450000h-045ffffh ba68 64 kwords 0440000h-044ffffh ba67 64 kwords 0430000h-043ffffh ba66 64 kwords 0420000h-042ffffh ba65 64 kwords 0410000h-041ffffh ba64 64 kwords 0400000h-040ffffh bank 14 ba63 64 kwords 03f0000h-03fffffh ba62 64 kwords 03e0000h-03effffh ba61 64 kwords 03d0000h-03dffffh ba60 64 kwords 03c0000h-03cffffh ba59 64 kwords 03b0000h-03bffffh ba58 64 kwords 03a0000h-03affffh ba57 64 kwords 0390000h-039ffffh ba56 64 kwords 0380000h-038ffffh ba55 64 kwords 0370000h-037ffffh ba54 64 kwords 0360000h-036ffffh ba53 64 kwords 0350000h-035ffffh ba52 64 kwords 0340000h-034ffffh ba51 64 kwords 0330000h-033ffffh ba50 64 kwords 0320000h-032ffffh ba49 64 kwords 0310000h-031ffffh ba48 64 kwords 0300000h-030ffffh ba47 64 kwords 02f0000h-02fffffh ba46 64 kwords 02e0000h-02effffh ba45 64 kwords 02d0000h-02dffffh ba44 64 kwords 02c0000h-02cffffh ba43 64 kwords 02b0000h-02bffffh ba42 64 kwords 02a0000h-02affffh ba41 64 kwords 0290000h-029ffffh ba40 64 kwords 0280000h-028ffffh ba39 64 kwords 0270000h-027ffffh ba38 64 kwords 0260000h-026ffffh ba37 64 kwords 0250000h-025ffffh ba36 64 kwords 0240000h-024ffffh ba35 64 kwords 0230000h-023ffffh - 60 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 18] top boot otp block addresses after entering otp block, any issued addresses should be in the range of otp block address. bank block block size (x16) address range bank 14 ba34 64 kwords 0220000h-022ffffh ba33 64 kwords 0210000h-021ffffh ba32 64 kwords 0200000h-020ffffh bank 15 ba31 64 kwords 01f0000h-01fffffh ba30 64 kwords 01e0000h-01effffh ba29 64 kwords 01d0000h-01dffffh ba28 64 kwords 01c0000h-01cffffh ba27 64 kwords 01b0000h-01bffffh ba26 64 kwords 01a0000h-01affffh ba25 64 kwords 0190000h-019ffffh ba24 64 kwords 0180000h-018ffffh ba23 64 kwords 0170000h-017ffffh ba22 64 kwords 0160000h-016ffffh ba21 64 kwords 0150000h-015ffffh ba20 64 kwords 0140000h-014ffffh ba19 64 kwords 0130000h-013ffffh ba18 64 kwords 0120000h-012ffffh ba17 64 kwords 0110000h-011ffffh ba16 64 kwords 0100000h-010ffffh ba15 64 kwords 00f0000h-00fffffh ba14 64 kwords 00e0000h-00effffh ba13 64 kwords 00d0000h-00dffffh ba12 64 kwords 00c0000h-00cffffh ba11 64 kwords 00b0000h-00bffffh ba10 64 kwords 00a0000h-00affffh ba9 64 kwords 0090000h-009ffffh ba8 64 kwords 0080000h-008ffffh ba7 64 kwords 0070000h-007ffffh ba6 64 kwords 0060000h-006ffffh ba5 64 kwords 0050000h-005ffffh ba4 64 kwords 0040000h-004ffffh ba3 64 kwords 0030000h-003ffffh ba2 64 kwords 0020000h-002ffffh ba1 64 kwords 0010000h-001ffffh ba0 64 kwords 0000000h-000ffffh otp block address a24 ~ a8 block size (x16) address range* 1ffffh 512 words 1fffe00h-1ffffffh - 61 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 19] bottom boot block address table bank block block size (x16) address range bank 15 ba514 64 kwords 1ff0000h-1ffffffh ba513 64 kwords 1fe0000h-1feffffh ba512 64 kwords 1fd0000h-1fdffffh ba511 64 kwords 1fc0000h-1fcffffh ba510 64 kwords 1fb0000h-1fbffffh ba509 64 kwords 1fa0000h-1faffffh ba508 64 kwords 1f90000h-1f9ffffh ba507 64 kwords 1f80000h-1f8ffffh ba506 64 kwords 1f70000h-1f7ffffh ba505 64 kwords 1f60000h-1f6ffffh ba504 64 kwords 1f50000h-1f5ffffh ba503 64 kwords 1f40000h-1f4ffffh ba502 64 kwords 1f30000h-1f3ffffh ba501 64 kwords 1f20000h-1f2ffffh ba500 64 kwords 1f10000h-1f1ffffh ba499 64 kwords 1f00000h-1f0ffffh ba498 64 kwords 1ef0000h-1efffffh ba497 64 kwords 1ee0000h-1eeffffh ba496 64 kwords 1ed0000h-1edffffh ba495 64 kwords 1ec0000h-1ecffffh ba494 64 kwords 1eb0000h-1ebffffh ba493 64 kwords 1ea0000h-1eaffffh ba492 64 kwords 1e90000h-1e9ffffh ba491 64 kwords 1e80000h-1e8ffffh ba490 64 kwords 1e70000h-1e7ffffh ba489 64 kwords 1e60000h-1e6ffffh ba488 64 kwords 1e50000h-1e5ffffh ba487 64 kwords 1e40000h-1e4ffffh ba486 64 kwords 1e30000h-1e3ffffh ba485 64 kwords 1e20000h-1e2ffffh ba484 64 kwords 1e10000h-1e1ffffh ba483 64 kwords 1e00000h-1e0ffffh bank 14 ba482 64 kwords 1df0000h-1dfffffh ba481 64 kwords 1de0000h-1deffffh ba480 64 kwords 1dd0000h-1ddffffh ba479 64 kwords 1dc0000h-1dcffffh ba478 64 kwords 1db0000h-1dbffffh ba477 64 kwords 1da0000h-1daffffh ba476 64 kwords 1d90000h-1d9ffffh ba475 64 kwords 1d80000h-1d8ffffh ba474 64 kwords 1d70000h-1d7ffffh ba473 64 kwords 1d60000h-1d6ffffh ba472 64 kwords 1d50000h-1d5ffffh ba471 64 kwords 1d40000h-1d4ffffh ba470 64 kwords 1d30000h-1d3ffffh - 62 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 14 ba469 64 kwords 1d20000h-1d2ffffh ba468 64 kwords 1d10000h-1d1ffffh ba467 64 kwords 1d00000h-1d0ffffh ba466 64 kwords 1cf0000h-1cfffffh ba465 64 kwords 1ce0000h-1ceffffh ba464 64 kwords 1cd0000h-1cdffffh ba463 64 kwords 1cc0000h-1ccffffh ba462 64 kwords 1cb0000h-1cbffffh ba461 64 kwords 1ca0000h-1caffffh ba460 64 kwords 1c90000h-1c9ffffh ba459 64 kwords 1c80000h-1c8ffffh ba458 64 kwords 1c70000h-1c7ffffh ba457 64 kwords 1c60000h-1c6ffffh ba456 64 kwords 1c50000h-1c5ffffh ba455 64 kwords 1c40000h-1c4ffffh ba454 64 kwords 1c30000h-1c3ffffh ba453 64 kwords 1c20000h-1c2ffffh ba452 64 kwords 1c10000h-1c1ffffh ba451 64 kwords 1c00000h-1c0ffffh bank 13 ba450 64 kwords 1bf0000h-1bfffffh ba449 64 kwords 1be0000h-1beffffh ba448 64 kwords 1bd0000h-1bdffffh ba447 64 kwords 1bc0000h-1bcffffh ba446 64 kwords 1bb0000h-1bbffffh ba445 64 kwords 1ba0000h-1baffffh ba444 64 kwords 1b90000h-1b9ffffh ba443 64 kwords 1b80000h-1b8ffffh ba442 64 kwords 1b70000h-1b7ffffh ba441 64 kwords 1b60000h-1b6ffffh ba440 64 kwords 1b50000h-1b5ffffh ba439 64 kwords 1b40000h-1b4ffffh ba438 64 kwords 1b30000h-1b3ffffh ba437 64 kwords 1b20000h-1b2ffffh ba436 64 kwords 1b10000h-1b1ffffh ba435 64 kwords 1b00000h-1b0ffffh ba434 64 kwords 1af0000h-1afffffh ba433 64 kwords 1ae0000h-1aeffffh ba432 64 kwords 1ad0000h-1adffffh ba431 64 kwords 1ac0000h-1acffffh ba430 64 kwords 1ab0000h-1abffffh ba429 64 kwords 1aa0000h-1aaffffh ba428 64 kwords 1a90000h-1a9ffffh ba427 64 kwords 1a80000h-1a8ffffh ba426 64 kwords 1a70000h-1a7ffffh ba425 64 kwords 1a60000h-1a6ffffh - 63 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 13 ba424 64 kwords 1a50000h-1a5ffffh ba423 64 kwords 1a40000h-1a4ffffh ba422 64 kwords 1a30000h-1a3ffffh ba421 64 kwords 1a20000h-1a2ffffh ba420 64 kwords 1a10000h-1a1ffffh ba419 64 kwords 1a00000h-1a0ffffh bank 12 ba418 64 kwords 19f0000h-19fffffh ba417 64 kwords 19e0000h-19effffh ba416 64 kwords 19d0000h-19dffffh ba415 64 kwords 19c0000h-19cffffh ba414 64 kwords 19b0000h-19bffffh ba413 64 kwords 19a0000h-19affffh ba412 64 kwords 1990000h-199ffffh ba411 64 kwords 1980000h-198ffffh ba410 64 kwords 1970000h-197ffffh ba409 64 kwords 1960000h-196ffffh ba408 64 kwords 1950000h-195ffffh ba407 64 kwords 1940000h-194ffffh ba406 64 kwords 1930000h-193ffffh ba405 64 kwords 1920000h-192ffffh ba404 64 kwords 1910000h-191ffffh ba403 64 kwords 1900000h-190ffffh ba402 64 kwords 18f0000h-18fffffh ba401 64 kwords 18e0000h-18effffh ba400 64 kwords 18d0000h-18dffffh ba399 64 kwords 18c0000h-18cffffh ba398 64 kwords 18b0000h-18bffffh ba397 64 kwords 18a0000h-18affffh ba396 64 kwords 1890000h-189ffffh ba395 64 kwords 1880000h-188ffffh ba394 64 kwords 1870000h-187ffffh ba393 64 kwords 1860000h-186ffffh ba392 64 kwords 1850000h-185ffffh ba391 64 kwords 1840000h-184ffffh ba390 64 kwords 1830000h-183ffffh ba389 64 kwords 1820000h-182ffffh ba388 64 kwords 1810000h-181ffffh ba387 64 kwords 1800000h-180ffffh bank 11 ba386 64 kwords 17f0000h-17fffffh ba385 64 kwords 17e0000h-17effffh ba384 64 kwords 17d0000h-17dffffh ba383 64 kwords 17c0000h-17cffffh ba382 64 kwords 17b0000h-17bffffh ba381 64 kwords 17a0000h-17affffh ba380 64 kwords 1790000h-179ffffh - 64 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 11 ba379 64 kwords 1780000h-178ffffh ba378 64 kwords 1770000h-177ffffh ba377 64 kwords 1760000h-176ffffh ba376 64 kwords 1750000h-175ffffh ba375 64 kwords 1740000h-174ffffh ba374 64 kwords 1730000h-173ffffh ba373 64 kwords 1720000h-172ffffh ba372 64 kwords 1710000h-171ffffh ba371 64 kwords 1700000h-170ffffh ba370 64 kwords 16f0000h-16fffffh ba369 64 kwords 16e0000h-16effffh ba368 64 kwords 16d0000h-16dffffh ba367 64 kwords 16c0000h-16cffffh ba366 64 kwords 16b0000h-16bffffh ba365 64 kwords 16a0000h-16affffh ba364 64 kwords 1690000h-169ffffh ba363 64 kwords 1680000h-168ffffh ba362 64 kwords 1670000h-167ffffh ba361 64 kwords 1660000h-166ffffh ba360 64 kwords 1650000h-165ffffh ba359 64 kwords 1640000h-164ffffh ba358 64 kwords 1630000h-163ffffh ba357 64 kwords 1620000h-162ffffh ba356 64 kwords 1610000h-161ffffh ba355 64 kwords 1600000h-160ffffh bank 10 ba354 64 kwords 15f0000h-15fffffh ba353 64 kwords 15e0000h-15effffh ba352 64 kwords 15d0000h-15dffffh ba351 64 kwords 15c0000h-15cffffh ba350 64 kwords 15b0000h-15bffffh ba349 64 kwords 15a0000h-15affffh ba348 64 kwords 1590000h-159ffffh ba347 64 kwords 1580000h-158ffffh ba346 64 kwords 1570000h-157ffffh ba345 64 kwords 1560000h-156ffffh ba344 64 kwords 1550000h-155ffffh ba343 64 kwords 1540000h-154ffffh ba342 64 kwords 1530000h-153ffffh ba341 64 kwords 1520000h-152ffffh ba340 64 kwords 1510000h-151ffffh ba339 64 kwords 1500000h-150ffffh ba338 64 kwords 14f0000h-14fffffh ba337 64 kwords 14e0000h-14effffh ba336 64 kwords 14d0000h-14dffffh - 65 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 10 ba335 64 kwords 14c0000h-14cffffh ba334 64 kwords 14b0000h-14bffffh ba333 64 kwords 14a0000h-14affffh ba332 64 kwords 1490000h-149ffffh ba331 64 kwords 1480000h-148ffffh ba330 64 kwords 1470000h-147ffffh ba329 64 kwords 1460000h-146ffffh ba328 64 kwords 1450000h-145ffffh ba327 64 kwords 1440000h-144ffffh ba326 64 kwords 1430000h-143ffffh ba325 64 kwords 1420000h-142ffffh ba324 64 kwords 1410000h-141ffffh ba323 64 kwords 1400000h-140ffffh bank 9 ba322 64 kwords 13f0000h-13fffffh ba321 64 kwords 13e0000h-13effffh ba320 64 kwords 13d0000h-13dffffh ba319 64 kwords 13c0000h-13cffffh ba318 64 kwords 13b0000h-13bffffh ba317 64 kwords 13a0000h-13affffh ba316 64 kwords 1390000h-139ffffh ba315 64 kwords 1380000h-138ffffh ba314 64 kwords 1370000h-137ffffh ba313 64 kwords 1360000h-136ffffh ba312 64 kwords 1350000h-135ffffh ba311 64 kwords 1340000h-134ffffh ba310 64 kwords 1330000h-133ffffh ba309 64 kwords 1320000h-132ffffh ba308 64 kwords 1310000h-131ffffh ba307 64 kwords 1300000h-130ffffh ba306 64 kwords 12f0000h-12fffffh ba305 64 kwords 12e0000h-12effffh ba304 64 kwords 12d0000h-12dffffh ba303 64 kwords 12c0000h-12cffffh ba302 64 kwords 12b0000h-12bffffh ba301 64 kwords 12a0000h-12affffh ba300 64 kwords 1290000h-129ffffh ba299 64 kwords 1280000h-128ffffh ba298 64 kwords 1270000h-127ffffh ba297 64 kwords 1260000h-126ffffh ba296 64 kwords 1250000h-125ffffh ba295 64 kwords 1240000h-124ffffh ba294 64 kwords 1230000h-123ffffh ba293 64 kwords 1220000h-122ffffh ba292 64 kwords 1210000h-121ffffh ba291 64 kwords 1200000h-120ffffh - 66 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 8 ba290 64 kwords 11f0000h-11fffffh ba289 64 kwords 11e0000h-11effffh ba288 64 kwords 11d0000h-11dffffh ba287 64 kwords 11c0000h-11cffffh ba286 64 kwords 11b0000h-11bffffh ba285 64 kwords 11a0000h-11affffh ba284 64 kwords 1190000h-119ffffh ba283 64 kwords 1180000h-118ffffh ba282 64 kwords 1170000h-117ffffh ba281 64 kwords 1160000h-116ffffh ba280 64 kwords 1150000h-115ffffh ba279 64 kwords 1140000h-114ffffh ba278 64 kwords 1130000h-113ffffh ba277 64 kwords 1120000h-112ffffh ba276 64 kwords 1110000h-111ffffh ba275 64 kwords 1100000h-110ffffh ba274 64 kwords 10f0000h-10fffffh ba273 64 kwords 10e0000h-10effffh ba272 64 kwords 10d0000h-10dffffh ba271 64 kwords 10c0000h-10cffffh ba270 64 kwords 10b0000h-10bffffh ba269 64 kwords 10a0000h-10affffh ba268 64 kwords 1090000h-109ffffh ba267 64 kwords 1080000h-108ffffh ba266 64 kwords 1070000h-107ffffh ba265 64 kwords 1060000h-106ffffh ba264 64 kwords 1050000h-105ffffh ba263 64 kwords 1040000h-104ffffh ba262 64 kwords 1030000h-103ffffh ba261 64 kwords 1020000h-102ffffh ba260 64 kwords 1010000h-101ffffh ba259 64 kwords 1000000h-100ffffh bank 7 ba258 64 kwords 0ff0000h-0ffffffh ba257 64 kwords 0fe0000h-0feffffh ba256 64 kwords 0fd0000h-0fdffffh ba255 64 kwords 0fc0000h-0fcffffh ba254 64 kwords 0fb0000h-0fbffffh ba253 64 kwords 0fa0000h-0faffffh ba252 64 kwords 0f90000h-0f9ffffh ba251 64 kwords 0f80000h-0f8ffffh ba250 64 kwords 0f70000h-0f7ffffh ba249 64 kwords 0f60000h-0f6ffffh ba248 64 kwords 0f50000h-0f5ffffh ba247 64 kwords 0f40000h-0f4ffffh ba246 64 kwords 0f30000h-0f3ffffh - 67 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 7 ba245 64 kwords 0f20000h-0f2ffffh ba244 64 kwords 0f10000h-0f1ffffh ba243 64 kwords 0f00000h-0f0ffffh ba242 64 kwords 0ef0000h-0efffffh ba241 64 kwords 0ee0000h-0eeffffh ba240 64 kwords 0ed0000h-0edffffh ba239 64 kwords 0ec0000h-0ecffffh ba238 64 kwords 0eb0000h-0ebffffh ba237 64 kwords 0ea0000h-0eaffffh ba236 64 kwords 0e90000h-0e9ffffh ba235 64 kwords 0e80000h-0e8ffffh ba234 64 kwords 0e70000h-0e7ffffh ba233 64 kwords 0e60000h-0e6ffffh ba232 64 kwords 0e50000h-0e5ffffh ba231 64 kwords 0e40000h-0e4ffffh ba230 64 kwords 0e30000h-0e3ffffh ba229 64 kwords 0e20000h-0e2ffffh ba228 64 kwords 0e10000h-0e1ffffh ba227 64 kwords 0e00000h-0e0ffffh bank 6 ba226 64 kwords 0df0000h-0dfffffh ba225 64 kwords 0de0000h-0deffffh ba224 64 kwords 0dd0000h-0ddffffh ba223 64 kwords 0dc0000h-0dcffffh ba222 64 kwords 0db0000h-0dbffffh ba221 64 kwords 0da0000h-0daffffh ba220 64 kwords 0d90000h-0d9ffffh ba219 64 kwords 0d80000h-0d8ffffh ba218 64 kwords 0d70000h-0d7ffffh ba217 64 kwords 0d60000h-0d6ffffh ba216 64 kwords 0d50000h-0d5ffffh ba215 64 kwords 0d40000h-0d4ffffh ba214 64 kwords 0d30000h-0d3ffffh ba213 64 kwords 0d20000h-0d2ffffh ba212 64 kwords 0d10000h-0d1ffffh ba211 64 kwords 0d00000h-0d0ffffh ba210 64 kwords 0cf0000h-0cfffffh ba209 64 kwords 0ce0000h-0ceffffh ba208 64 kwords 0cd0000h-0cdffffh ba207 64 kwords 0cc0000h-0ccffffh ba206 64 kwords 0cb0000h-0cbffffh ba205 64 kwords 0ca0000h-0caffffh ba204 64 kwords 0c90000h-0c9ffffh ba203 64 kwords 0c80000h-0c8ffffh ba202 64 kwords 0c70000h-0c7ffffh ba201 64 kwords 0c60000h-0c6ffffh - 68 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 6 ba200 64 kwords 0c50000h-0c5ffffh ba199 64 kwords 0c40000h-0c4ffffh ba198 64 kwords 0c30000h-0c3ffffh ba197 64 kwords 0c20000h-0c2ffffh ba196 64 kwords 0c10000h-0c1ffffh ba195 64 kwords 0c00000h-0c0ffffh bank 5 ba194 64 kwords 0bf0000h-0bfffffh ba193 64 kwords 0be0000h-0beffffh ba192 64 kwords 0bd0000h-0bdffffh ba191 64 kwords 0bc0000h-0bcffffh ba190 64 kwords 0bb0000h-0bbffffh ba189 64 kwords 0ba0000h-0baffffh ba188 64 kwords 0b90000h-0b9ffffh ba187 64 kwords 0b80000h-0b8ffffh ba186 64 kwords 0b70000h-0b7ffffh ba185 64 kwords 0b60000h-0b6ffffh ba184 64 kwords 0b50000h-0b5ffffh ba183 64 kwords 0b40000h-0b4ffffh ba182 64 kwords 0b30000h-0b3ffffh ba181 64 kwords 0b20000h-0b2ffffh ba180 64 kwords 0b10000h-0b1ffffh ba179 64 kwords 0b00000h-0b0ffffh ba178 64 kwords 0af0000h-0afffffh ba177 64 kwords 0ae0000h-0aeffffh ba176 64 kwords 0ad0000h-0adffffh ba175 64 kwords 0ac0000h-0acffffh ba174 64 kwords 0ab0000h-0abffffh ba173 64 kwords 0aa0000h-0aaffffh ba172 64 kwords 0a90000h-0a9ffffh ba171 64 kwords 0a80000h-0a8ffffh ba170 64 kwords 0a70000h-0a7ffffh ba169 64 kwords 0a60000h-0a6ffffh ba168 64 kwords 0a50000h-0a5ffffh ba167 64 kwords 0a40000h-0a4ffffh ba166 64 kwords 0a30000h-0a3ffffh ba165 64 kwords 0a20000h-0a2ffffh ba164 64 kwords 0a10000h-0a1ffffh ba163 64 kwords 0a00000h-0a0ffffh bank 4 ba162 64 kwords 09f0000h-09fffffh ba161 64 kwords 09e0000h-09effffh ba160 64 kwords 09d0000h-09dffffh ba159 64 kwords 09c0000h-09cffffh ba158 64 kwords 09b0000h-09bffffh ba157 64 kwords 09a0000h-09affffh ba156 64 kwords 0990000h-099ffffh - 69 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 4 ba155 64 kwords 0980000h-098ffffh ba154 64 kwords 0970000h-097ffffh ba153 64 kwords 0960000h-096ffffh ba152 64 kwords 0950000h-095ffffh ba151 64 kwords 0940000h-094ffffh ba150 64 kwords 0930000h-093ffffh ba149 64 kwords 0920000h-092ffffh ba148 64 kwords 0910000h-091ffffh ba147 64 kwords 0900000h-090ffffh ba146 64 kwords 08f0000h-08fffffh ba145 64 kwords 08e0000h-08effffh ba144 64 kwords 08d0000h-08dffffh ba143 64 kwords 08c0000h-08cffffh ba142 64 kwords 08b0000h-08bffffh ba141 64 kwords 08a0000h08affffh ba140 64 kwords 0890000h-089ffffh ba139 64 kwords 0880000h-088ffffh ba138 64 kwords 0870000h-087ffffh ba137 64 kwords 0860000h-086ffffh ba136 64 kwords 0850000h-085ffffh ba135 64 kwords 0840000h-084ffffh ba134 64 kwords 0830000h-083ffffh ba133 64 kwords 0820000h-082ffffh ba132 64 kwords 0810000h-081ffffh ba131 64 kwords 0800000h-080ffffh bank 3 ba130 64 kwords 07f0000h-07fffffh ba129 64 kwords 07e0000h-07effffh ba128 64 kwords 07d0000h-07dffffh ba127 64 kwords 07c0000h-07cffffh ba126 64 kwords 07b0000h-07bffffh ba125 64 kwords 07a0000h-07affffh ba124 64 kwords 0790000h-079ffffh ba123 64 kwords 0780000h-078ffffh ba122 64 kwords 0770000h-077ffffh ba121 64 kwords 0760000h-076ffffh ba120 64 kwords 0750000h-075ffffh ba119 64 kwords 0740000h-074ffffh ba118 64 kwords 0730000h-073ffffh ba117 64 kwords 0720000h-072ffffh ba116 64 kwords 0710000h-071ffffh ba115 64 kwords 0700000h-070ffffh ba114 64 kwords 06f0000h-06fffffh ba113 64 kwords 06e0000h-06effffh ba112 64 kwords 06d0000h-06dffffh ba111 64 kwords 06c0000h-06cffffh - 70 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 3 ba110 64 kwords 06b0000h-06bffffh ba109 64 kwords 06a0000h-06affffh ba108 64 kwords 0690000h-069ffffh ba107 64 kwords 0680000h-068ffffh ba106 64 kwords 0670000h-067ffffh ba105 64 kwords 0660000h-066ffffh ba104 64 kwords 0650000h-065ffffh ba103 64 kwords 0640000h-064ffffh ba102 64 kwords 0630000h-063ffffh ba101 64 kwords 0620000h-062ffffh ba100 64 kwords 0610000h-061ffffh ba99 64 kwords 0600000h-060ffffh bank 2 ba98 64 kwords 05f0000h-05fffffh ba97 64 kwords 05e0000h-05effffh ba96 64 kwords 05d0000h-05dffffh ba95 64 kwords 05c0000h-05cffffh ba94 64 kwords 05b0000h-05bffffh ba93 64 kwords 05a0000h-05affffh ba92 64 kwords 0590000h-059ffffh ba91 64 kwords 0580000h-058ffffh ba90 64 kwords 0570000h-057ffffh ba89 64 kwords 0560000h-056ffffh ba88 64 kwords 0550000h-055ffffh ba87 64 kwords 0540000h-054ffffh ba86 64 kwords 0530000h-053ffffh ba85 64 kwords 0520000h-052ffffh ba84 64 kwords 0510000h-051ffffh ba83 64 kwords 0500000h-050ffffh ba82 64 kwords 04f0000h-04fffffh ba81 64 kwords 04e0000h-04effffh ba80 64 kwords 04d0000h-04dffffh ba79 64 kwords 04c0000h-04cffffh ba78 64 kwords 04b0000h-04bffffh ba77 64 kwords 04a0000h-04affffh ba76 64 kwords 0490000h-049ffffh ba75 64 kwords 0480000h-048ffffh ba74 64 kwords 0470000h-047ffffh ba73 64 kwords 0460000h-046ffffh ba72 64 kwords 0450000h-045ffffh ba71 64 kwords 0440000h-044ffffh ba70 64 kwords 0430000h-043ffffh ba69 64 kwords 0420000h-042ffffh ba68 64 kwords 0410000h-041ffffh ba67 64 kwords 0400000h-040ffffh bank 1 ba66 64 kwords 03f0000h-03fffffh - 71 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 1 ba65 64 kwords 03e0000h-03effffh ba64 64 kwords 03d0000h-03dffffh ba63 64 kwords 03c0000h-03cffffh ba62 64 kwords 03b0000h-03bffffh ba61 64 kwords 03a0000h-03affffh ba60 64 kwords 0390000h-039ffffh ba59 64 kwords 0380000h-038ffffh ba58 64 kwords 0370000h-037ffffh ba57 64 kwords 0360000h-036ffffh ba56 64 kwords 0350000h-035ffffh ba55 64 kwords 0340000h-034ffffh ba54 64 kwords 0330000h-033ffffh ba53 64 kwords 0320000h-032ffffh ba52 64 kwords 0310000h-031ffffh ba51 64 kwords 0300000h-030ffffh ba50 64 kwords 02f0000h-02fffffh ba49 64 kwords 02e0000h-02effffh ba48 64 kwords 02d0000h-02dffffh ba47 64 kwords 02c0000h-02cffffh ba46 64 kwords 02b0000h-02bffffh ba45 64 kwords 02a0000h-02affffh ba44 64 kwords 0290000h-029ffffh ba43 64 kwords 0280000h-028ffffh ba42 64 kwords 0270000h-027ffffh ba41 64 kwords 0260000h-026ffffh ba40 64 kwords 0250000h-025ffffh ba39 64 kwords 0240000h-024ffffh ba38 64 kwords 0230000h-023ffffh ba37 64 kwords 0220000h-022ffffh ba36 64 kwords 0210000h-021ffffh ba35 64 kwords 0200000h-020ffffh bank 0 ba34 64 kwords 01f0000h-01fffffh ba33 64 kwords 01e0000h-01effffh ba32 64 kwords 01d0000h-01dffffh ba31 64 kwords 01c0000h-01cffffh ba30 64 kwords 01b0000h-01bffffh ba29 64 kwords 01a0000h-01affffh ba28 64 kwords 0190000h-019ffffh ba27 64 kwords 0180000h-018ffffh ba26 64 kwords 0170000h-017ffffh ba25 64 kwords 0160000h-016ffffh ba24 64 kwords 0150000h-015ffffh ba23 64 kwords 0140000h-014ffffh ba22 64 kwords 0130000h-013ffffh ba21 64 kwords 0120000h-012ffffh - 72 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 20] bottom boot otp block addresses after entering otp block, any issued addresses should be in the range of otp block address. bank block block size (x16) address range bank 0 ba20 64 kwords 0110000h-011ffffh ba19 64 kwords 0100000h-010ffffh ba18 64 kwords 00f0000h-00fffffh ba17 64 kwords 00e0000h-00effffh ba16 64 kwords 00d0000h-00dffffh ba15 64 kwords 00c0000h-00cffffh ba14 64 kwords 00b0000h-00bffffh ba13 64 kwords 00a0000h-00affffh ba12 64 kwords 0090000h-009ffffh ba11 64 kwords 0080000h-008ffffh ba10 64 kwords 0070000h-007ffffh ba9 64 kwords 0060000h-006ffffh ba8 64 kwords 0050000h-005ffffh ba7 64 kwords 0040000h-004ffffh ba6 64 kwords 0030000h-003ffffh ba5 64 kwords 0020000h-002ffffh ba4 64 kwords 0010000h-001ffffh ba3 16 kwords 000c000h-000ffffh ba2 16 kwords 0008000h-000bfffh ba1 16 kwords 0004000h-0007fffh ba0 16 kwords 0000000h-0003fffh otp block address a24 ~ a8 block size (x16) address range* 00000h 512 words 0000000h-00001ffh - 73 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 21] uniform block address table bank block block size (x16) address range bank 0 ba511 64 kwords 1ff0000h-1ffffffh ba510 64 kwords 1fe0000h-1feffffh ba509 64 kwords 1fd0000h-1fdffffh ba508 64 kwords 1fc0000h-1fcffffh ba507 64 kwords 1fb0000h-1fbffffh ba506 64 kwords 1fa0000h-1faffffh ba505 64 kwords 1f90000h-1f9ffffh ba504 64 kwords 1f80000h-1f8ffffh ba503 64 kwords 1f70000h-1f7ffffh ba502 64 kwords 1f60000h-1f6ffffh ba501 64 kwords 1f50000h-1f5ffffh ba500 64 kwords 1f40000h-1f4ffffh ba499 64 kwords 1f30000h-1f3ffffh ba498 64 kwords 1f20000h-1f2ffffh ba497 64 kwords 1f10000h-1f1ffffh ba496 64 kwords 1f00000h-1f0ffffh ba495 64 kwords 1ef0000h-1efffffh ba494 64 kwords 1ee0000h-1eeffffh ba493 64 kwords 1ed0000h-1edffffh ba492 64 kwords 1ec0000h-1ecffffh ba491 64 kwords 1eb0000h-1ebffffh ba490 64 kwords 1ea0000h-1eaffffh ba489 64 kwords 1e90000h-1e9ffffh ba488 64 kwords 1e80000h-1e8ffffh ba487 64 kwords 1e70000h-1e7ffffh ba486 64 kwords 1e60000h-1e6ffffh ba485 64 kwords 1e50000h-1e5ffffh ba484 64 kwords 1e40000h-1e4ffffh ba483 64 kwords 1e30000h-1e3ffffh ba482 64 kwords 1e20000h-1e2ffffh ba481 64 kwords 1e10000h-1e1ffffh ba480 64 kwords 1e00000h-1e0ffffh bank 1 ba479 64 kwords 1df0000h-1dfffffh ba478 64 kwords 1de0000h-1deffffh ba477 64 kwords 1dd0000h-1ddffffh ba476 64 kwords 1dc0000h-1dcffffh ba475 64 kwords 1db0000h-1dbffffh ba474 64 kwords 1da0000h-1daffffh ba473 64 kwords 1d90000h-1d9ffffh ba472 64 kwords 1d80000h-1d8ffffh ba471 64 kwords 1d70000h-1d7ffffh ba470 64 kwords 1d60000h-1d6ffffh - 74 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 1 ba469 64 kwords 1d50000h-1d5ffffh ba468 64 kwords 1d40000h-1d4ffffh ba467 64 kwords 1d30000h-1d3ffffh ba466 64 kwords 1d20000h-1d2ffffh ba465 64 kwords 1d10000h-1d1ffffh ba464 64 kwords 1d00000h-1d0ffffh ba463 64 kwords 1cf0000h-1cfffffh ba462 64 kwords 1ce0000h-1ceffffh ba461 64 kwords 1cd0000h-1cdffffh ba460 64 kwords 1cc0000h-1ccffffh ba459 64 kwords 1cb0000h-1cbffffh ba458 64 kwords 1ca0000h-1caffffh ba457 64 kwords 1c90000h-1c9ffffh ba456 64 kwords 1c80000h-1c8ffffh ba455 64 kwords 1c70000h-1c7ffffh ba454 64 kwords 1c60000h-1c6ffffh ba453 64 kwords 1c50000h-1c5ffffh ba452 64 kwords 1c40000h-1c4ffffh ba451 64 kwords 1c30000h-1c3ffffh ba450 64 kwords 1c20000h-1c2ffffh ba449 64 kwords 1c10000h-1c1ffffh ba448 64 kwords 1c00000h-1c0ffffh bank 2 ba447 64 kwords 1bf0000h-1bfffffh ba446 64 kwords 1be0000h-1beffffh ba445 64 kwords 1bd0000h-1bdffffh ba444 64 kwords 1bc0000h-1bcffffh ba443 64 kwords 1bb0000h-1bbffffh ba442 64 kwords 1ba0000h-1baffffh ba441 64 kwords 1b90000h-1b9ffffh ba440 64 kwords 1b80000h-1b8ffffh ba439 64 kwords 1b70000h-1b7ffffh ba438 64 kwords 1b60000h-1b6ffffh ba437 64 kwords 1b50000h-1b5ffffh ba436 64 kwords 1b40000h-1b4ffffh ba435 64 kwords 1b30000h-1b3ffffh ba434 64 kwords 1b20000h-1b2ffffh ba433 64 kwords 1b10000h-1b1ffffh ba432 64 kwords 1b00000h-1b0ffffh ba431 64 kwords 1af0000h-1afffffh ba430 64 kwords 1ae0000h-1aeffffh ba429 64 kwords 1ad0000h-1adffffh ba428 64 kwords 1ac0000h-1acffffh ba427 64 kwords 1ab0000h-1abffffh ba426 64 kwords 1aa0000h-1aaffffh ba425 64 kwords 1a90000h-1a9ffffh - 75 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 2 ba424 64 kwords 1a80000h-1a8ffffh ba423 64 kwords 1a70000h-1a7ffffh ba422 64 kwords 1a60000h-1a6ffffh ba421 64 kwords 1a50000h-1a5ffffh ba420 64 kwords 1a40000h-1a4ffffh ba419 64 kwords 1a30000h-1a3ffffh ba418 64 kwords 1a20000h-1a2ffffh ba417 64 kwords 1a10000h-1a1ffffh ba416 64 kwords 1a00000h-1a0ffffh bank 3 ba415 64 kwords 19f0000h-19fffffh ba414 64 kwords 19e0000h-19effffh ba413 64 kwords 19d0000h-19dffffh ba412 64 kwords 19c0000h-19cffffh ba411 64 kwords 19b0000h-19bffffh ba410 64 kwords 19a0000h-19affffh ba409 64 kwords 1990000h-199ffffh ba408 64 kwords 1980000h-198ffffh ba407 64 kwords 1970000h-197ffffh ba406 64 kwords 1960000h-196ffffh ba405 64 kwords 1950000h-195ffffh ba404 64 kwords 1940000h-194ffffh ba403 64 kwords 1930000h-193ffffh ba402 64 kwords 1920000h-192ffffh ba401 64 kwords 1910000h-191ffffh ba400 64 kwords 1900000h-190ffffh ba399 64 kwords 18f0000h-18fffffh ba398 64 kwords 18e0000h-18effffh ba397 64 kwords 18d0000h-18dffffh ba396 64 kwords 18c0000h-18cffffh ba395 64 kwords 18b0000h-18bffffh ba394 64 kwords 18a0000h-18affffh ba393 64 kwords 1890000h-189ffffh ba392 64 kwords 1880000h-188ffffh ba391 64 kwords 1870000h-187ffffh ba390 64 kwords 1860000h-186ffffh ba389 64 kwords 1850000h-185ffffh ba388 64 kwords 1840000h-184ffffh ba387 64 kwords 1830000h-183ffffh ba386 64 kwords 1820000h-182ffffh ba385 64 kwords 1810000h-181ffffh ba384 64 kwords 1800000h-180ffffh bank 4 ba383 64 kwords 17f0000h-17fffffh ba382 64 kwords 17e0000h-17effffh ba381 64 kwords 17d0000h-17dffffh ba380 64 kwords 17c0000h-17cffffh - 76 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 4 ba379 64 kwords 17b0000h-17bffffh ba378 64 kwords 17a0000h-17affffh ba377 64 kwords 1790000h-179ffffh ba376 64 kwords 1780000h-178ffffh ba375 64 kwords 1770000h-177ffffh ba374 64 kwords 1760000h-176ffffh ba373 64 kwords 1750000h-175ffffh ba372 64 kwords 1740000h-174ffffh ba371 64 kwords 1730000h-173ffffh ba370 64 kwords 1720000h-172ffffh ba369 64 kwords 1710000h-171ffffh ba368 64 kwords 1700000h-170ffffh ba367 64 kwords 16f0000h-16fffffh ba366 64 kwords 16e0000h-16effffh ba365 64 kwords 16d0000h-16dffffh ba364 64 kwords 16c0000h-16cffffh ba363 64 kwords 16b0000h-16bffffh ba362 64 kwords 16a0000h-16affffh ba361 64 kwords 1690000h-169ffffh ba360 64 kwords 1680000h-168ffffh ba359 64 kwords 1670000h-167ffffh ba358 64 kwords 1660000h-166ffffh ba357 64 kwords 1650000h-165ffffh ba356 64 kwords 1640000h-164ffffh ba355 64 kwords 1630000h-163ffffh ba354 64 kwords 1620000h-162ffffh ba353 64 kwords 1610000h-161ffffh ba352 64 kwords 1600000h-160ffffh bank5 ba351 64 kwords 15f0000h-15fffffh ba350 64 kwords 15e0000h-15effffh ba349 64 kwords 15d0000h-15dffffh ba348 64 kwords 15c0000h-15cffffh ba347 64 kwords 15b0000h-15bffffh ba346 64 kwords 15a0000h-15affffh ba345 64 kwords 1590000h-159ffffh ba344 64 kwords 1580000h-158ffffh ba343 64 kwords 1570000h-157ffffh ba342 64 kwords 1560000h-156ffffh ba341 64 kwords 1550000h-155ffffh ba340 64 kwords 1540000h-154ffffh ba339 64 kwords 1530000h-153ffffh ba338 64 kwords 1520000h-152ffffh ba337 64 kwords 1510000h-151ffffh ba336 64 kwords 1500000h-150ffffh - 77 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 5 ba335 64 kwords 14f0000h-14fffffh ba334 64 kwords 14e0000h-14effffh ba333 64 kwords 14d0000h-14dffffh ba332 64 kwords 14c0000h-14cffffh ba331 64 kwords 14b0000h-14bffffh ba330 64 kwords 14a0000h-14affffh ba329 64 kwords 1490000h-149ffffh ba328 64 kwords 1480000h-148ffffh ba327 64 kwords 1470000h-147ffffh ba326 64 kwords 1460000h-146ffffh ba325 64 kwords 1450000h-145ffffh ba324 64 kwords 1440000h-144ffffh ba323 64 kwords 1430000h-143ffffh ba322 64 kwords 1420000h-142ffffh ba321 64 kwords 1410000h-141ffffh ba320 64 kwords 1400000h-140ffffh bank 6 ba319 64 kwords 13f0000h-13fffffh ba318 64 kwords 13e0000h-13effffh ba317 64 kwords 13d0000h-13dffffh ba316 64 kwords 13c0000h-13cffffh ba315 64 kwords 13b0000h-13bffffh ba314 64 kwords 13a0000h-13affffh ba313 64 kwords 1390000h-139ffffh ba312 64 kwords 1380000h-138ffffh ba311 64 kwords 1370000h-137ffffh ba310 64 kwords 1360000h-136ffffh ba309 64 kwords 1350000h-135ffffh ba308 64 kwords 1340000h-134ffffh ba307 64 kwords 1330000h-133ffffh ba306 64 kwords 1320000h-132ffffh ba305 64 kwords 1310000h-131ffffh ba304 64 kwords 1300000h-130ffffh ba303 64 kwords 12f0000h-12fffffh ba302 64 kwords 12e0000h-12effffh ba301 64 kwords 12d0000h-12dffffh ba300 64 kwords 12c0000h-12cffffh ba299 64 kwords 12b0000h-12bffffh ba298 64 kwords 12a0000h-12affffh ba297 64 kwords 1290000h-129ffffh ba296 64 kwords 1280000h-128ffffh ba295 64 kwords 1270000h-127ffffh ba294 64 kwords 1260000h-126ffffh ba293 64 kwords 1250000h-125ffffh ba292 64 kwords 1240000h-124ffffh ba291 64 kwords 1230000h-123ffffh - 78 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 6 ba290 64 kwords 1220000h-122ffffh ba289 64 kwords 1210000h-121ffffh ba288 64 kwords 1200000h-120ffffh bank 7 ba287 64 kwords 11f0000h-11fffffh ba286 64 kwords 11e0000h-11effffh ba285 64 kwords 11d0000h-11dffffh ba284 64 kwords 11c0000h-11cffffh ba283 64 kwords 11b0000h-11bffffh ba282 64 kwords 11a0000h-11affffh ba281 64 kwords 1190000h-119ffffh ba280 64 kwords 1180000h-118ffffh ba279 64 kwords 1170000h-117ffffh ba278 64 kwords 1160000h-116ffffh ba277 64 kwords 1150000h-115ffffh ba276 64 kwords 1140000h-114ffffh ba275 64 kwords 1130000h-113ffffh ba274 64 kwords 1120000h-112ffffh ba273 64 kwords 1110000h-111ffffh ba272 64 kwords 1100000h-110ffffh ba271 64 kwords 10f0000h-10fffffh ba270 64 kwords 10e0000h-10effffh ba269 64 kwords 10d0000h-10dffffh ba268 64 kwords 10c0000h-10cffffh ba267 64 kwords 10b0000h-10bffffh ba266 64 kwords 10a0000h-10affffh ba265 64 kwords 1090000h-109ffffh ba264 64 kwords 1080000h-108ffffh ba263 64 kwords 1070000h-107ffffh ba262 64 kwords 1060000h-106ffffh ba261 64 kwords 1050000h-105ffffh ba260 64 kwords 1040000h-104ffffh ba259 64 kwords 1030000h-103ffffh - 79 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 7 ba258 64 kwords 1020000h-102ffffh ba257 64 kwords 1010000h-101ffffh ba256 64 kwords 1000000h-100ffffh bank 8 ba255 64 kwords 0ff0000h-0ffffffh ba254 64 kwords 0fe0000h-0feffffh ba253 64 kwords 0fd0000h-0fdffffh ba252 64 kwords 0fc0000h-0fcffffh ba251 64 kwords 0fb0000h-0fbffffh ba250 64 kwords 0fa0000h-0faffffh ba249 64 kwords 0f90000h-0f9ffffh ba248 64 kwords 0f80000h-0f8ffffh ba247 64 kwords 0f70000h-0f7ffffh ba246 64 kwords 0f60000h-0f6ffffh ba245 64 kwords 0f50000h-0f5ffffh ba244 64 kwords 0f40000h-0f4ffffh ba243 64 kwords 0f30000h-0f3ffffh ba242 64 kwords 0f20000h-0f2ffffh ba241 64 kwords 0f10000h-0f1ffffh ba240 64 kwords 0f00000h-0f0ffffh ba239 64 kwords 0ef0000h-0efffffh ba238 64 kwords 0ee0000h-0eeffffh ba237 64 kwords 0ed0000h-0edffffh ba236 64 kwords 0ec0000h-0ecffffh ba235 64 kwords 0eb0000h-0ebffffh ba234 64 kwords 0ea0000h-0eaffffh ba233 64 kwords 0e90000h-0e9ffffh ba232 64 kwords 0e80000h-0e8ffffh ba231 64 kwords 0e70000h-0e7ffffh ba230 64 kwords 0e60000h-0e6ffffh ba229 64 kwords 0e50000h-0e5ffffh ba228 64 kwords 0e40000h-0e4ffffh ba227 64 kwords 0e30000h-0e3ffffh ba226 64 kwords 0e20000h-0e2ffffh ba225 64 kwords 0e10000h-0e1ffffh ba224 64 kwords 0e00000h-0e0ffffh bank 9 ba223 64 kwords 0df0000h-0dfffffh ba222 64 kwords 0de0000h-0deffffh ba221 64 kwords 0dd0000h-0ddffffh ba220 64 kwords 0dc0000h-0dcffffh ba219 64 kwords 0db0000h-0dbffffh ba218 64 kwords 0da0000h-0daffffh ba217 64 kwords 0d90000h-0d9ffffh ba216 64 kwords 0d80000h-0d8ffffh ba215 64 kwords 0d70000h-0d7ffffh ba214 64 kwords 0d60000h-0d6ffffh - 80 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 9 ba213 64 kwords 0d50000h-0d5ffffh ba212 64 kwords 0d40000h-0d4ffffh ba211 64 kwords 0d30000h-0d3ffffh ba210 64 kwords 0d20000h-0d2ffffh ba209 64 kwords 0d10000h-0d1ffffh ba208 64 kwords 0d00000h-0d0ffffh ba207 64 kwords 0cf0000h-0cfffffh ba206 64 kwords 0ce0000h-0ceffffh ba205 64 kwords 0cd0000h-0cdffffh ba204 64 kwords 0cc0000h-0ccffffh ba203 64 kwords 0cb0000h-0cbffffh ba202 64 kwords 0ca0000h-0caffffh ba201 64 kwords 0c90000h-0c9ffffh ba200 64 kwords 0c80000h-0c8ffffh ba199 64 kwords 0c70000h-0c7ffffh ba198 64 kwords 0c60000h-0c6ffffh ba197 64 kwords 0c50000h-0c5ffffh ba196 64 kwords 0c40000h-0c4ffffh ba195 64 kwords 0c30000h-0c3ffffh ba194 64 kwords 0c20000h-0c2ffffh ba193 64 kwords 0c10000h-0c1ffffh ba192 64 kwords 0c00000h-0c0ffffh bank 10 ba191 64 kwords 0bf0000h-0bfffffh ba190 64 kwords 0be0000h-0beffffh ba189 64 kwords 0bd0000h-0bdffffh ba188 64 kwords 0bc0000h-0bcffffh ba187 64 kwords 0bb0000h-0bbffffh ba186 64 kwords 0ba0000h-0baffffh ba185 64 kwords 0b90000h-0b9ffffh ba184 64 kwords 0b80000h-0b8ffffh ba183 64 kwords 0b70000h-0b7ffffh ba182 64 kwords 0b60000h-0b6ffffh ba181 64 kwords 0b50000h-0b5ffffh ba180 64 kwords 0b40000h-0b4ffffh ba179 64 kwords 0b30000h-0b3ffffh ba178 64 kwords 0b20000h-0b2ffffh ba177 64 kwords 0b10000h-0b1ffffh ba176 64 kwords 0b00000h-0b0ffffh ba175 64 kwords 0af0000h-0afffffh ba174 64 kwords 0ae0000h-0aeffffh ba173 64 kwords 0ad0000h-0adffffh ba172 64 kwords 0ac0000h-0acffffh ba171 64 kwords 0ab0000h-0abffffh ba170 64 kwords 0aa0000h-0aaffffh ba169 64 kwords 0a90000h-0a9ffffh - 81 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 10 ba168 64 kwords 0a80000h-0a8ffffh ba167 64 kwords 0a70000h-0a7ffffh ba166 64 kwords 0a60000h-0a6ffffh ba165 64 kwords 0a50000h-0a5ffffh ba164 64 kwords 0a40000h-0a4ffffh ba163 64 kwords 0a30000h-0a3ffffh ba162 64 kwords 0a20000h-0a2ffffh ba161 64 kwords 0a10000h-0a1ffffh ba160 64 kwords 0a00000h-0a0ffffh bank 11 ba159 64 kwords 09f0000h-09fffffh ba158 64 kwords 09e0000h-09effffh ba157 64 kwords 09d0000h-09dffffh ba156 64 kwords 09c0000h-09cffffh ba155 64 kwords 09b0000h-09bffffh ba154 64 kwords 09a0000h-09affffh ba153 64 kwords 0990000h-099ffffh ba152 64 kwords 0980000h-098ffffh ba151 64 kwords 0970000h-097ffffh ba150 64 kwords 0960000h-096ffffh ba149 64 kwords 0950000h-095ffffh ba148 64 kwords 0940000h-094ffffh ba147 64 kwords 0930000h-093ffffh ba146 64 kwords 0920000h-092ffffh ba145 64 kwords 0910000h-091ffffh ba144 64 kwords 0900000h-090ffffh ba143 64 kwords 08f0000h-08fffffh ba142 64 kwords 08e0000h-08effffh ba141 64 kwords 08d0000h-08dffffh ba140 64 kwords 08c0000h-08cffffh ba139 64 kwords 08b0000h-08bffffh ba138 64 kwords 08a0000h-08affffh ba137 64 kwords 0890000h-089ffffh ba136 64 kwords 0880000h-088ffffh ba135 64 kwords 0870000h-087ffffh ba134 64 kwords 0860000h-086ffffh ba133 64 kwords 0850000h-085ffffh ba132 64 kwords 0840000h-084ffffh ba131 64 kwords 0830000h-083ffffh ba130 64 kwords 0820000h-082ffffh ba129 64 kwords 0810000h-081ffffh ba128 64 kwords 0800000h-080ffffh bank 12 ba127 64 kwords 07f0000h-07fffffh ba126 64 kwords 07e0000h-07effffh ba125 64 kwords 07d0000h-07dffffh ba124 64 kwords 07c0000h-07cffffh - 82 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 12 ba123 64 kwords 07b0000h-07bffffh ba122 64 kwords 07a0000h-07affffh ba121 64 kwords 0790000h-079ffffh ba120 64 kwords 0780000h-078ffffh ba119 64 kwords 0770000h-077ffffh ba118 64 kwords 0760000h-076ffffh ba117 64 kwords 0750000h-075ffffh ba116 64 kwords 0740000h-074ffffh ba115 64 kwords 0730000h-073ffffh ba114 64 kwords 0720000h-072ffffh ba113 64 kwords 0710000h-071ffffh ba112 64 kwords 0700000h-070ffffh ba111 64 kwords 06f0000h-06fffffh ba110 64 kwords 06e0000h-06effffh ba109 64 kwords 06d0000h-06dffffh ba108 64 kwords 06c0000h-06cffffh ba107 64 kwords 06b0000h-06bffffh ba106 64 kwords 06a0000h-06affffh ba105 64 kwords 0690000h-069ffffh ba104 64 kwords 0680000h-068ffffh ba103 64 kwords 0670000h-067ffffh ba102 64 kwords 0660000h-066ffffh ba101 64 kwords 0650000h-065ffffh ba100 64 kwords 0640000h-064ffffh ba99 64 kwords 0630000h-063ffffh ba98 64 kwords 0620000h-062ffffh ba97 64 kwords 0610000h-061ffffh ba96 64 kwords 0600000h-060ffffh bank13 ba95 64 kwords 05f0000h-05fffffh ba94 64 kwords 05e0000h-05effffh ba93 64 kwords 05d0000h-05dffffh ba92 64 kwords 05c0000h-05cffffh ba91 64 kwords 05b0000h-05bffffh ba90 64 kwords 05a0000h-05affffh ba89 64 kwords 0590000h-059ffffh ba88 64 kwords 0580000h-058ffffh ba87 64 kwords 0570000h-057ffffh ba86 64 kwords 0560000h-056ffffh ba85 64 kwords 0550000h-055ffffh ba84 64 kwords 0540000h-054ffffh ba83 64 kwords 0530000h-053ffffh ba82 64 kwords 0520000h-052ffffh ba81 64 kwords 0510000h-051ffffh ba80 64 kwords 0500000h-050ffffh - 83 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 bank block block size (x16) address range bank 13 ba79 64 kwords 04f0000h-04fffffh ba78 64 kwords 04e0000h-04effffh ba77 64 kwords 04d0000h-04dffffh ba76 64 kwords 04c0000h-04cffffh ba75 64 kwords 04b0000h-04bffffh ba74 64 kwords 04a0000h-04affffh ba73 64 kwords 0490000h-049ffffh ba72 64 kwords 0480000h-048ffffh ba71 64 kwords 0470000h-047ffffh ba70 64 kwords 0460000h-046ffffh ba69 64 kwords 0450000h-045ffffh ba68 64 kwords 0440000h-044ffffh ba67 64 kwords 0430000h-043ffffh ba66 64 kwords 0420000h-042ffffh ba65 64 kwords 0410000h-041ffffh ba64 64 kwords 0400000h-040ffffh bank 14 ba63 64 kwords 03f0000h-03fffffh ba62 64 kwords 03e0000h-03effffh ba61 64 kwords 03d0000h-03dffffh ba60 64 kwords 03c0000h-03cffffh ba59 64 kwords 03b0000h-03bffffh ba58 64 kwords 03a0000h-03affffh ba57 64 kwords 0390000h-039ffffh ba56 64 kwords 0380000h-038ffffh ba55 64 kwords 0370000h-037ffffh ba54 64 kwords 0360000h-036ffffh ba53 64 kwords 0350000h-035ffffh ba52 64 kwords 0340000h-034ffffh ba51 64 kwords 0330000h-033ffffh ba50 64 kwords 0320000h-032ffffh ba49 64 kwords 0310000h-031ffffh ba48 64 kwords 0300000h-030ffffh ba47 64 kwords 02f0000h-02fffffh ba46 64 kwords 02e0000h-02effffh ba45 64 kwords 02d0000h-02dffffh ba44 64 kwords 02c0000h-02cffffh ba43 64 kwords 02b0000h-02bffffh ba42 64 kwords 02a0000h-02affffh ba41 64 kwords 0290000h-029ffffh ba40 64 kwords 0280000h-028ffffh ba39 64 kwords 0270000h-027ffffh ba38 64 kwords 0260000h-026ffffh ba37 64 kwords 0250000h-025ffffh ba36 64 kwords 0240000h-024ffffh ba35 64 kwords 0230000h-023ffffh - 84 - k8a12(13)15et(b/z)c datasheet nor flash memory rev. 1.1 [table 22] uniform otp block addresses after entering otp block, any issued addresses should be in the range of otp block address. bank block block size (x16) address range bank 14 ba34 64 kwords 0220000h-022ffffh ba33 64 kwords 0210000h-021ffffh ba32 64 kwords 0200000h-020ffffh bank 15 ba31 64 kwords 01f0000h-01fffffh ba30 64 kwords 01e0000h-01effffh ba29 64 kwords 01d0000h-01dffffh ba28 64 kwords 01c0000h-01cffffh ba27 64 kwords 01b0000h-01bffffh ba26 64 kwords 01a0000h-01affffh ba25 64 kwords 0190000h-019ffffh ba24 64 kwords 0180000h-018ffffh ba23 64 kwords 0170000h-017ffffh ba22 64 kwords 0160000h-016ffffh ba21 64 kwords 0150000h-015ffffh ba20 64 kwords 0140000h-014ffffh ba19 64 kwords 0130000h-013ffffh ba18 64 kwords 0120000h-012ffffh ba17 64 kwords 0110000h-011ffffh ba16 64 kwords 0100000h-010ffffh ba15 64 kwords 00f0000h-00fffffh ba14 64 kwords 00e0000h-00effffh ba13 64 kwords 00d0000h-00dffffh ba12 64 kwords 00c0000h-00cffffh ba11 64 kwords 00b0000h-00bffffh ba10 64 kwords 00a0000h-00affffh ba9 64 kwords 0090000h-009ffffh ba8 64 kwords 0080000h-008ffffh ba7 64 kwords 0070000h-007ffffh ba6 64 kwords 0060000h-006ffffh ba5 64 kwords 0050000h-005ffffh ba4 64 kwords 0040000h-004ffffh ba3 64 kwords 0030000h-003ffffh ba2 64 kwords 0020000h-002ffffh ba1 64 kwords 0010000h-001ffffh ba0 64 kwords 0000000h-000ffffh otp block address a24 ~ a8 block size (x16) address range* 1ffffh 512 words 1fffe00h-1ffffffh |
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